M7350/kernel/Documentation/devicetree/bindings/media/video/msm-ispif.txt

* Qualcomm MSM ISPIF

Required properties:
- cell-index: ispif hardware core index
- compatible :
    - "qcom,ispif"
    - "qcom,ispif-v3.0"
- reg : offset and length of the register set for the device
    for the ispif operating in compatible mode.
- reg-names : should specify relevant names to each reg property defined.
- interrupts : should contain the ispif interrupt.
- interrupt-names : should specify relevant names to each interrupts
  property defined.
- camss-vdd-supply: phandle to GDSC regulator.
- mmagic-vdd-supply: phandle to mmagic regulator.
- vfe0-vdd-supply: phandle to vfe0 regulator.
- vfe1-vdd-supply: phandle to vfe1 regulator.
- clocks: list of phandles to the clock controller device and coresponding
  clock names.
- clock-names: name of the clocks required for the device used by the consumer.
- qcom,clock-rates: clock rate in Hz.
- qcom,clock-control: The valid fields are "NO_SET_RATE", "INIT_RATE" and
  "SET_RATE". "NO_SET_RATE" the corresponding clock is enabled without setting
  the rate assuming some other driver has already set it to appropriate rate.
  "INIT_RATE" clock rate is not queried assuming some other driver has set
  the clock rate and ispif will set the the clock to this rate.
  "SET_RATE" clock is enabled and the rate is set to the value specified
  in the property qcom,clock-rates.

Optional properties:
- qcom,num-isps: The number of ISPs the ISPIF module is connected to. If not set
  the default value used is 1

Example:

	qcom,ispif@fda0a000 {
	cell-index = <0>;
	compatible = "qcom,ispif";
	reg = <0xfda0a000 0x300>;
	reg-names = "ispif";
	interrupts = <0 55 0>;
	interrupt-names = "ispif";
	camss-vdd-supply = <&gdsc_camss_top>;
	mmagic-vdd-supply = <&gdsc_mmagic_camss>;
	vfe0-vdd-supply = <&gdsc_vfe0>;
	vfe1-vdd-supply = <&gdsc_vfe1>;
	clocks = <&clock_mmss clk_camss_ispif_ahb_clk>,
		<&clock_mmss clk_csi0_clk_src>,
		<&clock_mmss clk_camss_csi0_clk>,
		<&clock_mmss clk_camss_csi0rdi_clk>,
		<&clock_mmss clk_camss_csi0pix_clk>,
		<&clock_mmss clk_csi1_clk_src>,
		<&clock_mmss clk_camss_csi1_clk>,
		<&clock_mmss clk_camss_csi1rdi_clk>,
		<&clock_mmss clk_camss_csi1pix_clk>,
		<&clock_mmss clk_csi2_clk_src>,
		<&clock_mmss clk_camss_csi2_clk>,
		<&clock_mmss clk_camss_csi2rdi_clk>,
		<&clock_mmss clk_camss_csi2pix_clk>,
		<&clock_mmss clk_csi3_clk_src>,
		<&clock_mmss clk_camss_csi3_clk>,
		<&clock_mmss clk_camss_csi3rdi_clk>,
		<&clock_mmss clk_camss_csi3pix_clk>,
		<&clock_mmss clk_vfe0_clk_src>,
		<&clock_mmss clk_camss_vfe0_clk>,
		<&clock_mmss clk_camss_csi_vfe0_clk>,
		<&clock_mmss clk_vfe1_clk_src>,
		<&clock_mmss clk_camss_vfe1_clk>,
		<&clock_mmss clk_camss_csi_vfe1_clk>;
	clock-names = "ispif_ahb_clk",
		"csi0_src_clk", "csi0_clk",
		"csi0_pix_clk", "csi0_rdi_clk",
		"csi1_src_clk", "csi1_clk",
		"csi1_pix_clk", "csi1_rdi_clk",
		"csi2_src_clk", "csi2_clk",
		"csi2_pix_clk", "csi2_rdi_clk",
		"csi3_src_clk", "csi3_clk",
		"csi3_pix_clk", "csi3_rdi_clk",
		"vfe0_clk_src", "camss_vfe_vfe0_clk", "camss_csi_vfe0_clk",
		"vfe1_clk_src", "camss_vfe_vfe1_clk", "camss_csi_vfe1_clk";
	qcom,clock-rates = <0
		200000000 0 0 0
		200000000 0 0 0
		200000000 0 0 0
		200000000 0 0 0
		0 0 0
		0 0 0>;
	qcom,clock-control = "NO_SET_RATE",
		"SET_RATE", "NO_SET_RATE", "NO_SET_RATE", "NO_SET_RATE",
		"SET_RATE", "NO_SET_RATE", "NO_SET_RATE", "NO_SET_RATE",
		"SET_RATE", "NO_SET_RATE", "NO_SET_RATE", "NO_SET_RATE",
		"SET_RATE", "NO_SET_RATE", "NO_SET_RATE", "NO_SET_RATE",
		"INIT_RATE", "NO_SET_RATE", "NO_SET_RATE",
		"INIT_RATE", "NO_SET_RATE", "NO_SET_RATE";

	};

or

	qcom,ispif@fda0a000 {
	cell-index = <0>;
	compatible = "qcom,ispif-v3.0", "qcom,ispif";
	reg = <0xfda0a000 0x300>;
	reg-names = "ispif";
	interrupts = <0 55 0>;
	interrupt-names = "ispif";
	qcom,num-isps = <2>
	vdd-supply = <&gdsc_camss_top>;
	clocks = <&clock_mmss clk_camss_ispif_ahb_clk>,
		<&clock_mmss clk_csi0_clk_src>,
		<&clock_mmss clk_camss_csi0_clk>,
		<&clock_mmss clk_camss_csi0rdi_clk>,
		<&clock_mmss clk_camss_csi0pix_clk>,
		<&clock_mmss clk_csi1_clk_src>,
		<&clock_mmss clk_camss_csi1_clk>,
		<&clock_mmss clk_camss_csi1rdi_clk>,
		<&clock_mmss clk_camss_csi1pix_clk>,
		<&clock_mmss clk_csi2_clk_src>,
		<&clock_mmss clk_camss_csi2_clk>,
		<&clock_mmss clk_camss_csi2rdi_clk>,
		<&clock_mmss clk_camss_csi2pix_clk>,
		<&clock_mmss clk_csi3_clk_src>,
		<&clock_mmss clk_camss_csi3_clk>,
		<&clock_mmss clk_camss_csi3rdi_clk>,
		<&clock_mmss clk_camss_csi3pix_clk>,
		<&clock_mmss clk_vfe0_clk_src>,
		<&clock_mmss clk_camss_vfe0_clk>,
		<&clock_mmss clk_camss_csi_vfe0_clk>,
		<&clock_mmss clk_vfe1_clk_src>,
		<&clock_mmss clk_camss_vfe1_clk>,
		<&clock_mmss clk_camss_csi_vfe1_clk>;
	clock-names = "ispif_ahb_clk",
		"csi0_src_clk", "csi0_clk",
		"csi0_pix_clk", "csi0_rdi_clk",
		"csi1_src_clk", "csi1_clk",
		"csi1_pix_clk", "csi1_rdi_clk",
		"csi2_src_clk", "csi2_clk",
		"csi2_pix_clk", "csi2_rdi_clk",
		"csi3_src_clk", "csi3_clk",
		"csi3_pix_clk", "csi3_rdi_clk",
		"vfe0_clk_src", "camss_vfe_vfe0_clk", "camss_csi_vfe0_clk",
		"vfe1_clk_src", "camss_vfe_vfe1_clk", "camss_csi_vfe1_clk";
	qcom,clock-rates = <0
		200000000 0 0 0
		200000000 0 0 0
		200000000 0 0 0
		200000000 0 0 0
		0 0 0
		0 0 0>;
	qcom,clock-control = "NO_SET_RATE",
		"SET_RATE", "NO_SET_RATE", "NO_SET_RATE", "NO_SET_RATE",
		"SET_RATE", "NO_SET_RATE", "NO_SET_RATE", "NO_SET_RATE",
		"SET_RATE", "NO_SET_RATE", "NO_SET_RATE", "NO_SET_RATE",
		"SET_RATE", "NO_SET_RATE", "NO_SET_RATE", "NO_SET_RATE",
		"INIT_RATE", "NO_SET_RATE", "NO_SET_RATE",
		"INIT_RATE", "NO_SET_RATE", "NO_SET_RATE";

	};