50 lines
1.3 KiB
Plaintext
50 lines
1.3 KiB
Plaintext
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Binding for a ST divider and multiplexer clock driver.
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This binding uses the common clock binding[1].
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Base address is located to the parent node. See clock binding[2]
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[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
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[2] Documentation/devicetree/bindings/clock/st/st,clkgen.txt
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Required properties:
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- compatible : shall be:
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"st,clkgena-divmux-c65-hs", "st,clkgena-divmux"
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"st,clkgena-divmux-c65-ls", "st,clkgena-divmux"
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"st,clkgena-divmux-c32-odf0", "st,clkgena-divmux"
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"st,clkgena-divmux-c32-odf1", "st,clkgena-divmux"
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"st,clkgena-divmux-c32-odf2", "st,clkgena-divmux"
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"st,clkgena-divmux-c32-odf3", "st,clkgena-divmux"
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- #clock-cells : From common clock binding; shall be set to 1.
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- clocks : From common clock binding
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- clock-output-names : From common clock binding.
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Example:
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clockgen-a@fd345000 {
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reg = <0xfd345000 0xb50>;
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clk_m_a1_div1: clk-m-a1-div1 {
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#clock-cells = <1>;
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compatible = "st,clkgena-divmux-c32-odf1",
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"st,clkgena-divmux";
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clocks = <&clk_m_a1_osc_prediv>,
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<&clk_m_a1_pll0 1>, /* PLL0 PHI1 */
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<&clk_m_a1_pll1 1>; /* PLL1 PHI1 */
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clock-output-names = "clk-m-rx-icn-ts",
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"clk-m-rx-icn-vdp-0",
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"", /* unused */
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"clk-m-prv-t1-bus",
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"clk-m-icn-reg-12",
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"clk-m-icn-reg-10",
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"", /* unused */
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"clk-m-icn-st231";
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};
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};
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