21 lines
524 B
Plaintext
21 lines
524 B
Plaintext
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L2 cache performance monitor unit
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L2 cache controllers have a performance monitor unit to measure
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events such as cache hits and misses. There is one L2 cache PMU
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for each cluster of CPUs.
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Required properties:
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- compatible : should be "qcom,qcom-l2cache-pmu"
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- interrupts : 1 interrupt for each cluster.
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- qcom,cpu-affinity: specifies the id of the first CPU in the cluster.
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Example:
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l2cache-pmu {
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compatible = "qcom,qcom-l2cache-pmu";
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interrupts = <0 0 1>, <0 8 1>;
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qcom,cpu-affinity = <0>, <2>
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};
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