65 lines
2.4 KiB
Plaintext
65 lines
2.4 KiB
Plaintext
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Qualcomm MSMTITANIUM CPU clock tree
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clock-cpu-titanium is a device that represents the MSMTITANIUM CPU subystem clock
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tree. It lists the various power supplies that need to be scaled when the
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clocks are scaled and also other HW specific parameters like fmax tables etc.
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The root clock generator could have the ramp controller in built.
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Ramp control will allow programming the sequence ID for pulse swallowing,
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enable sequence and for linking sequence IDs.
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Required properties:
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- compatible: Must be "qcom,clock-cpu-titanium".
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- reg: Pairs of physical base addresses and region sizes of
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memory mapped registers.
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- reg-names: Names of the bases for the above registers. Expected
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bases are:
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"c0-pll", "c1-pll", "c0-mux", "c1-mux", "cci-mux",
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"efuse", "perf_base"(optional), "rcgwr-c0-base(optional)",
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"rcgwr-c1-base(optional)".
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- clocks: The clocks sources used by the cluster/cci mux.
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- clock-names: Name of the clocks for the above clocks.
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- vdd-mx-supply: The regulator powering all the PLLs of clusters & cci.
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- vdd-cl-supply: The regulator powering the clusters & cci.
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- qcom,speedX-bin-vY-ZZZ:
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A table of CPU frequency (Hz) to voltage (corner)
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mapping that represents the max frequency possible
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for each supported voltage level for a CPU. 'X' is
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the speed bin into which the device falls into - a
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bin will have unique frequency-voltage relationships.
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'Y' is the characterization version, implying that
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characterization (deciding what speed bin a device
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falls into) methods and/or encoding may change. The
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values 'X' and 'Y' are read from efuse registers, and
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the right table is picked from multiple possible tables.
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'ZZZ' can be cl for(c0 & c1) or cci depending on whether
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the table for the clusters or cci.
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Example:
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clock_cpu: qcom,cpu-clock-titanium@b116000 {
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compatible = "qcom,cpu-clock-titanium";
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reg = <0xb114000 0x68>,
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<0xb014000 0x68>,
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<0xb116000 0x400>,
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<0xb111050 0x08>,
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<0xb011050 0x08>,
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<0xb1d1050 0x08>,
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<0x00a412c 0x08>;
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reg-names = "rcgwr-c0-base", "rcgwr-c1-base",
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"c0-pll", "c0-mux", "c1-mux",
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"cci-mux", "efuse";
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vdd-mx-supply = <&pmtitanium_s7_level_ao>;
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vdd-cl-supply = <&apc_vreg_corner>;
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clocks = <&clock_gcc clk_xo_a_clk_src>;
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clock-names = "xo_a";
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qcom,num-clusters = <2>;
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qcom,speed0-bin-v0-cl =
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< 0 0>,
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< 2208000000 7>;
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qcom,speed0-bin-v0-cci =
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< 0 0>,
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< 883200000 7>;
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#address-cells = <1>;
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#size-cells = <1>;
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};
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