79 lines
2.9 KiB
Plaintext
79 lines
2.9 KiB
Plaintext
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Qualcomm MSM 8996 CPU clock tree
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clock-cpu-8996 is a device that represents the MSM 8996 CPU subsystem
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clock tree. It lists the various power supplies that need to be scaled when
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the clocks are scaled and also other HW specific parameters like fmax tables,
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PLL FMAXes etc.
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Required properties:
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- compatible: Must be either "qcom,cpu-clock-8996" or
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"qcom,cpu-clock-8996-v3"
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- reg: Pairs of physical base addresses and region sizes of
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memory mapped registers.
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- reg-names: Names of the bases for the above registers. Expected
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bases are:
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"pwrcl_pll", "perfcl_pll", "cbf_pll", "pwrcl_mux",
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"perfcl_mux", "cbf_mux", "efuse";
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- vdd-perfcl-supply: The regulator powering the power cluster
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- vdd-pwrcl-supply: The regulator powering the perf cluster
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- vdd-cbf-supply: The regulator powering the CBF interconnect
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- vdd-dig-supply: The regulator powering the cluster PLLs
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- qcom,pwrcl-speedbinY-vZ:
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A table of CPU frequency (Hz) to voltage (corner)
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mapping that represents the max frequency possible
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for each supported voltage level for the power cluster.
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'Y' is the speed bin into which the device falls into -
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a bin will have unique frequency-voltage relationships.
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'Z' is the characterization version, implying that
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characterization (deciding what speed bin a device
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falls into) methods and/or encoding may change. The
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values 'Y' and 'Z' are read from efuse registers, and
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the right table is picked from multiple possible tables.
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- qcom,perfcl-speedbinY-vZ:
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Similar to the qcom,pwrcl-speedbinY-vZ property above,
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except this frequency to voltage table is applied to the
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clock for the perf cluster.
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- qcom,cbf-speedbinY-vZ:
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Similar to the qcom,perfcl-speedbinY-vZ property above,
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except this frequency to voltage table is applied to the
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clock for the CBF.
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- cbf-dev: The CBF cache device to which the OPP table for the
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CBF clock domain will be added.
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Example:
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clock_cpu: qcom,cpu-clock-8996@ {
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compatible = "qcom,cpu-clock-8996";
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reg = <0x06400000 0x1000>,
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<0x06480000 0x1000>,
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<0x09A20000 0x1000>,
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<0x06400000 0x1000>,
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<0x06480000 0x1000>,
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<0x09A11000 0x1000>,
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<0x00070130 0x8>;
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reg-names = "pwrcl_pll", "perfcl_pll", "cbf_pll", "pwrcl_mux", "perfcl_mux", "cbf_mux", "efuse";
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vdd-pwrcl-supply = <&apc_vreg_corner>;
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vdd-perfcl-supply = <&apc_vreg_corner>;
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vdd-cbf-supply = <&apc_vreg_corner>;
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vdd-dig-supply = <&pm8994_s1_corner_ao>;
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qcom,pwrcl-speedbin0-v0 =
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< 0 0 >,
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< 300000000 1 >,
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< 345600000 2 >,
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< 422400000 3 >,
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< 1459200000 18 >;
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qcom,perfcl-speedbin0-v0 =
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< 0 0 >,
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< 300000000 1 >,
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< 345600000 2 >,
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< 422400000 3 >,
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< 1593600000 18 >;
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qcom,cbf-speedbin0-v0 =
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< 0 0 >,
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< 300000000 1 >,
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< 384000000 3 >,
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< 1036800000 18 >;
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clock-names = "xo_ao", "aux_clk";
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clocks = <&clock_gcc clk_cxo_clk_src_ao>,
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<&clock_gcc clk_gpll0_out_main>;
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#clock-cells = <1>;
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};
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