623 lines
15 KiB
C
623 lines
15 KiB
C
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/*
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* Copyright (c) 2004-2011 Atheros Communications Inc.
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*/
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#include "core.h"
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#include "hif-ops.h"
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#include "target.h"
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#include "debug.h"
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int ath6kl_bmi_done(struct ath6kl *ar)
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{
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int ret;
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u32 cid = BMI_DONE;
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u32 endianBuf32;
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if (ar->bmi.done_sent) {
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ath6kl_dbg(ATH6KL_DBG_BMI, "bmi done skipped\n");
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return 0;
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}
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ar->bmi.done_sent = true;
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endianBuf32 = cpu_to_le32(cid);
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ret = ath6kl_hif_bmi_write(ar, (u8 *)&endianBuf32, sizeof(endianBuf32));
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if (ret) {
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ath6kl_err("Unable to send bmi done: %d\n", ret);
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return ret;
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}
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return 0;
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}
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int ath6kl_bmi_get_target_info(struct ath6kl *ar,
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struct ath6kl_bmi_target_info *targ_info)
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{
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int ret;
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u32 cid = BMI_GET_TARGET_INFO;
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u32 endianBuf32;
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if (ar->bmi.done_sent) {
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ath6kl_err("bmi done sent already, cmd %d disallowed\n", cid);
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return -EACCES;
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}
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endianBuf32 = cpu_to_le32(cid);
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ret = ath6kl_hif_bmi_write(ar, (u8 *)&endianBuf32, sizeof(endianBuf32));
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if (ret) {
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ath6kl_err("Unable to send get target info: %d\n", ret);
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return ret;
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}
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if (ar->hif_type == ATH6KL_HIF_TYPE_USB) {
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ret = ath6kl_hif_bmi_read(ar, (u8 *)targ_info,
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sizeof(*targ_info));
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} else {
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ret = ath6kl_hif_bmi_read(ar, (u8 *)&targ_info->version,
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sizeof(targ_info->version));
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}
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if (ret) {
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ath6kl_err("Unable to recv target info: %d\n", ret);
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return ret;
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}
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if (le32_to_cpu(targ_info->version) == TARGET_VERSION_SENTINAL) {
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/* Determine how many bytes are in the Target's targ_info */
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ret = ath6kl_hif_bmi_read(ar,
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(u8 *)&targ_info->byte_count,
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sizeof(targ_info->byte_count));
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if (ret) {
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ath6kl_err("unable to read target info byte count: %d\n",
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ret);
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return ret;
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}
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/*
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* The target's targ_info doesn't match the host's targ_info.
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* We need to do some backwards compatibility to make this work.
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*/
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if (le32_to_cpu(targ_info->byte_count) != sizeof(*targ_info)) {
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WARN_ON(1);
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return -EINVAL;
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}
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/* Read the remainder of the targ_info */
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ret = ath6kl_hif_bmi_read(ar,
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((u8 *)targ_info) +
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sizeof(targ_info->byte_count),
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sizeof(*targ_info) -
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sizeof(targ_info->byte_count));
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if (ret) {
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ath6kl_err("Unable to read target info (%d bytes): %d\n",
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le32_to_cpu(targ_info->byte_count), ret);
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return ret;
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}
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}
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ath6kl_dbg(ATH6KL_DBG_BMI, "target info (ver: 0x%x type: 0x%x)\n",
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le32_to_cpu(targ_info->version), le32_to_cpu(targ_info->type));
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return 0;
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}
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int ath6kl_bmi_read(struct ath6kl *ar, u32 addr, u8 *buf, u32 len)
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{
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u32 cid = BMI_READ_MEMORY;
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int ret;
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u32 offset;
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u32 len_remain, rx_len;
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u16 size;
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u32 endianBuf32;
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if (ar->bmi.done_sent) {
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ath6kl_err("bmi done sent already, cmd %d disallowed\n", cid);
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return -EACCES;
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}
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size = ar->bmi.max_data_size + sizeof(cid) + sizeof(addr) + sizeof(len);
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if (size > ar->bmi.max_cmd_size) {
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WARN_ON(1);
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return -EINVAL;
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}
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memset(ar->bmi.cmd_buf, 0, size);
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ath6kl_dbg(ATH6KL_DBG_BMI,
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"bmi read memory: device: addr: 0x%x, len: %d\n",
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addr, len);
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len_remain = len;
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while (len_remain) {
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rx_len = (len_remain < ar->bmi.max_data_size) ?
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len_remain : ar->bmi.max_data_size;
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offset = 0;
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endianBuf32 = cpu_to_le32(cid);
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memcpy(&(ar->bmi.cmd_buf[offset]), &endianBuf32,
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sizeof(endianBuf32));
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offset += sizeof(cid);
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endianBuf32 = cpu_to_le32(addr);
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memcpy(&(ar->bmi.cmd_buf[offset]), &endianBuf32,
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sizeof(endianBuf32));
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offset += sizeof(addr);
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endianBuf32 = cpu_to_le32(rx_len);
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memcpy(&(ar->bmi.cmd_buf[offset]), &endianBuf32,
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sizeof(endianBuf32));
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offset += sizeof(len);
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ret = ath6kl_hif_bmi_write(ar, ar->bmi.cmd_buf, offset);
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if (ret) {
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ath6kl_err("Unable to write to the device: %d\n",
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ret);
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return ret;
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}
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ret = ath6kl_hif_bmi_read(ar, ar->bmi.cmd_buf, rx_len);
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if (ret) {
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ath6kl_err("Unable to read from the device: %d\n",
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ret);
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return ret;
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}
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memcpy(&buf[len - len_remain], ar->bmi.cmd_buf, rx_len);
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len_remain -= rx_len; addr += rx_len;
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}
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#ifdef __BIG_ENDIAN
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if (len == 4) {
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u32 buf_tmp;
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memcpy(&buf_tmp, buf, sizeof(u32));
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buf_tmp = le32_to_cpu(buf_tmp);
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memcpy(buf, &buf_tmp, sizeof(u32));
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}
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#endif
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return 0;
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}
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int ath6kl_bmi_write(struct ath6kl *ar, u32 addr, u8 *buf, u32 len)
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{
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u32 cid = BMI_WRITE_MEMORY;
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int ret;
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u32 offset;
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u32 len_remain, tx_len;
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const u32 header = sizeof(cid) + sizeof(addr) + sizeof(len);
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u8 aligned_buf[400];
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u8 *src;
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u32 endianBuf32;
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if (ar->bmi.done_sent) {
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ath6kl_err("bmi done sent already, cmd %d disallowed\n", cid);
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return -EACCES;
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}
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if ((ar->bmi.max_data_size + header) > ar->bmi.max_cmd_size) {
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WARN_ON(1);
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return -EINVAL;
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}
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if (WARN_ON(ar->bmi.max_data_size > sizeof(aligned_buf)))
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return -E2BIG;
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memset(ar->bmi.cmd_buf, 0, ar->bmi.max_data_size + header);
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ath6kl_dbg(ATH6KL_DBG_BMI,
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"bmi write memory: addr: 0x%x, len: %d\n", addr, len);
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len_remain = len;
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while (len_remain) {
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src = &buf[len - len_remain];
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if (len_remain < (ar->bmi.max_data_size - header)) {
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if (len_remain & 3) {
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/* align it with 4 bytes */
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len_remain = len_remain +
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(4 - (len_remain & 3));
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memcpy(aligned_buf, src, len_remain);
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src = aligned_buf;
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}
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tx_len = len_remain;
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} else {
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tx_len = (ar->bmi.max_data_size - header);
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}
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offset = 0;
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endianBuf32 = cpu_to_le32(cid);
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memcpy(&(ar->bmi.cmd_buf[offset]), &endianBuf32,
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sizeof(endianBuf32));
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offset += sizeof(cid);
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endianBuf32 = cpu_to_le32(addr);
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memcpy(&(ar->bmi.cmd_buf[offset]), &endianBuf32,
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sizeof(endianBuf32));
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offset += sizeof(addr);
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endianBuf32 = cpu_to_le32(tx_len);
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memcpy(&(ar->bmi.cmd_buf[offset]), &endianBuf32,
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sizeof(endianBuf32));
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offset += sizeof(tx_len);
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if (len == 4) {
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endianBuf32 = cpu_to_le32(*((u32 *)src));
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memcpy(&(ar->bmi.cmd_buf[offset]), &endianBuf32,
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sizeof(endianBuf32));
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} else {
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memcpy(&(ar->bmi.cmd_buf[offset]), src, tx_len);
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}
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offset += tx_len;
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ret = ath6kl_hif_bmi_write(ar, ar->bmi.cmd_buf, offset);
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if (ret) {
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ath6kl_err("Unable to write to the device: %d\n",
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ret);
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return ret;
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}
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len_remain -= tx_len; addr += tx_len;
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}
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return 0;
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}
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int ath6kl_bmi_execute(struct ath6kl *ar, u32 addr, u32 *param)
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{
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u32 cid = BMI_EXECUTE;
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int ret;
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u32 offset;
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u16 size;
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u32 endianBuf32;
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if (ar->bmi.done_sent) {
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ath6kl_err("bmi done sent already, cmd %d disallowed\n", cid);
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return -EACCES;
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}
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size = sizeof(cid) + sizeof(addr) + sizeof(param);
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if (size > ar->bmi.max_cmd_size) {
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WARN_ON(1);
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return -EINVAL;
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}
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memset(ar->bmi.cmd_buf, 0, size);
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ath6kl_dbg(ATH6KL_DBG_BMI, "bmi execute: addr: 0x%x, param: %d)\n",
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addr, *param);
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offset = 0;
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endianBuf32 = cpu_to_le32(cid);
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memcpy(&(ar->bmi.cmd_buf[offset]), &endianBuf32, sizeof(endianBuf32));
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offset += sizeof(cid);
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endianBuf32 = cpu_to_le32(addr);
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memcpy(&(ar->bmi.cmd_buf[offset]), &endianBuf32, sizeof(endianBuf32));
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offset += sizeof(addr);
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endianBuf32 = cpu_to_le32(*param);
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memcpy(&(ar->bmi.cmd_buf[offset]), &endianBuf32, sizeof(endianBuf32));
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offset += sizeof(*param);
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ret = ath6kl_hif_bmi_write(ar, ar->bmi.cmd_buf, offset);
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if (ret) {
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ath6kl_err("Unable to write to the device: %d\n", ret);
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return ret;
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}
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ret = ath6kl_hif_bmi_read(ar, ar->bmi.cmd_buf, sizeof(*param));
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if (ret) {
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ath6kl_err("Unable to read from the device: %d\n", ret);
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return ret;
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}
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memcpy(param, ar->bmi.cmd_buf, sizeof(*param));
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#ifdef __BIG_ENDIAN
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{
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u32 buf_tmp;
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memcpy(&buf_tmp, param, sizeof(u32));
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buf_tmp = le32_to_cpu(buf_tmp);
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memcpy(param, &buf_tmp, sizeof(u32));
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}
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#endif
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return 0;
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}
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int ath6kl_bmi_set_app_start(struct ath6kl *ar, u32 addr)
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{
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u32 cid = BMI_SET_APP_START;
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int ret;
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u32 offset;
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u16 size;
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u32 endianBuf32;
|
||
|
|
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if (ar->bmi.done_sent) {
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ath6kl_err("bmi done sent already, cmd %d disallowed\n", cid);
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return -EACCES;
|
||
|
}
|
||
|
|
||
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size = sizeof(cid) + sizeof(addr);
|
||
|
if (size > ar->bmi.max_cmd_size) {
|
||
|
WARN_ON(1);
|
||
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return -EINVAL;
|
||
|
}
|
||
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memset(ar->bmi.cmd_buf, 0, size);
|
||
|
|
||
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ath6kl_dbg(ATH6KL_DBG_BMI, "bmi set app start: addr: 0x%x\n", addr);
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|
|
||
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offset = 0;
|
||
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endianBuf32 = cpu_to_le32(cid);
|
||
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memcpy(&(ar->bmi.cmd_buf[offset]), &endianBuf32, sizeof(endianBuf32));
|
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offset += sizeof(cid);
|
||
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endianBuf32 = cpu_to_le32(addr);
|
||
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memcpy(&(ar->bmi.cmd_buf[offset]), &endianBuf32, sizeof(endianBuf32));
|
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|
offset += sizeof(addr);
|
||
|
|
||
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ret = ath6kl_hif_bmi_write(ar, ar->bmi.cmd_buf, offset);
|
||
|
if (ret) {
|
||
|
ath6kl_err("Unable to write to the device: %d\n", ret);
|
||
|
return ret;
|
||
|
}
|
||
|
|
||
|
return 0;
|
||
|
}
|
||
|
|
||
|
int ath6kl_bmi_reg_read(struct ath6kl *ar, u32 addr, u32 *param)
|
||
|
{
|
||
|
u32 cid = BMI_READ_SOC_REGISTER;
|
||
|
int ret;
|
||
|
u32 offset;
|
||
|
u16 size;
|
||
|
u32 endianBuf32;
|
||
|
|
||
|
if (ar->bmi.done_sent) {
|
||
|
ath6kl_err("bmi done sent already, cmd %d disallowed\n", cid);
|
||
|
return -EACCES;
|
||
|
}
|
||
|
|
||
|
size = sizeof(cid) + sizeof(addr);
|
||
|
if (size > ar->bmi.max_cmd_size) {
|
||
|
WARN_ON(1);
|
||
|
return -EINVAL;
|
||
|
}
|
||
|
memset(ar->bmi.cmd_buf, 0, size);
|
||
|
|
||
|
ath6kl_dbg(ATH6KL_DBG_BMI, "bmi read SOC reg: addr: 0x%x\n", addr);
|
||
|
|
||
|
offset = 0;
|
||
|
endianBuf32 = cpu_to_le32(cid);
|
||
|
memcpy(&(ar->bmi.cmd_buf[offset]), &endianBuf32, sizeof(endianBuf32));
|
||
|
offset += sizeof(cid);
|
||
|
endianBuf32 = cpu_to_le32(addr);
|
||
|
memcpy(&(ar->bmi.cmd_buf[offset]), &endianBuf32, sizeof(endianBuf32));
|
||
|
offset += sizeof(addr);
|
||
|
|
||
|
ret = ath6kl_hif_bmi_write(ar, ar->bmi.cmd_buf, offset);
|
||
|
if (ret) {
|
||
|
ath6kl_err("Unable to write to the device: %d\n", ret);
|
||
|
return ret;
|
||
|
}
|
||
|
|
||
|
ret = ath6kl_hif_bmi_read(ar, ar->bmi.cmd_buf, sizeof(*param));
|
||
|
if (ret) {
|
||
|
ath6kl_err("Unable to read from the device: %d\n", ret);
|
||
|
return ret;
|
||
|
}
|
||
|
memcpy(param, ar->bmi.cmd_buf, sizeof(*param));
|
||
|
|
||
|
#ifdef __BIG_ENDIAN
|
||
|
{
|
||
|
u32 buf_tmp;
|
||
|
|
||
|
memcpy(&buf_tmp, param, sizeof(u32));
|
||
|
buf_tmp = le32_to_cpu(buf_tmp);
|
||
|
memcpy(param, &buf_tmp, sizeof(u32));
|
||
|
}
|
||
|
#endif
|
||
|
|
||
|
return 0;
|
||
|
}
|
||
|
|
||
|
int ath6kl_bmi_reg_write(struct ath6kl *ar, u32 addr, u32 param)
|
||
|
{
|
||
|
u32 cid = BMI_WRITE_SOC_REGISTER;
|
||
|
int ret;
|
||
|
u32 offset;
|
||
|
u16 size;
|
||
|
u32 endianBuf32;
|
||
|
|
||
|
if (ar->bmi.done_sent) {
|
||
|
ath6kl_err("bmi done sent already, cmd %d disallowed\n", cid);
|
||
|
return -EACCES;
|
||
|
}
|
||
|
|
||
|
size = sizeof(cid) + sizeof(addr) + sizeof(param);
|
||
|
if (size > ar->bmi.max_cmd_size) {
|
||
|
WARN_ON(1);
|
||
|
return -EINVAL;
|
||
|
}
|
||
|
memset(ar->bmi.cmd_buf, 0, size);
|
||
|
|
||
|
ath6kl_dbg(ATH6KL_DBG_BMI,
|
||
|
"bmi write SOC reg: addr: 0x%x, param: %d\n",
|
||
|
addr, param);
|
||
|
|
||
|
offset = 0;
|
||
|
endianBuf32 = cpu_to_le32(cid);
|
||
|
memcpy(&(ar->bmi.cmd_buf[offset]), &endianBuf32, sizeof(endianBuf32));
|
||
|
offset += sizeof(cid);
|
||
|
endianBuf32 = cpu_to_le32(addr);
|
||
|
memcpy(&(ar->bmi.cmd_buf[offset]), &endianBuf32, sizeof(endianBuf32));
|
||
|
offset += sizeof(addr);
|
||
|
endianBuf32 = cpu_to_le32(param);
|
||
|
memcpy(&(ar->bmi.cmd_buf[offset]), &endianBuf32, sizeof(endianBuf32));
|
||
|
offset += sizeof(param);
|
||
|
|
||
|
ret = ath6kl_hif_bmi_write(ar, ar->bmi.cmd_buf, offset);
|
||
|
if (ret) {
|
||
|
ath6kl_err("Unable to write to the device: %d\n", ret);
|
||
|
return ret;
|
||
|
}
|
||
|
|
||
|
return 0;
|
||
|
}
|
||
|
|
||
|
int ath6kl_bmi_lz_data(struct ath6kl *ar, u8 *buf, u32 len)
|
||
|
{
|
||
|
u32 cid = BMI_LZ_DATA;
|
||
|
int ret;
|
||
|
u32 offset;
|
||
|
u32 len_remain, tx_len;
|
||
|
const u32 header = sizeof(cid) + sizeof(len);
|
||
|
u16 size;
|
||
|
u32 endianBuf32;
|
||
|
|
||
|
if (ar->bmi.done_sent) {
|
||
|
ath6kl_err("bmi done sent already, cmd %d disallowed\n", cid);
|
||
|
return -EACCES;
|
||
|
}
|
||
|
|
||
|
size = ar->bmi.max_data_size + header;
|
||
|
if (size > ar->bmi.max_cmd_size) {
|
||
|
WARN_ON(1);
|
||
|
return -EINVAL;
|
||
|
}
|
||
|
memset(ar->bmi.cmd_buf, 0, size);
|
||
|
|
||
|
ath6kl_dbg(ATH6KL_DBG_BMI, "bmi send LZ data: len: %d)\n",
|
||
|
len);
|
||
|
|
||
|
len_remain = len;
|
||
|
while (len_remain) {
|
||
|
tx_len = (len_remain < (ar->bmi.max_data_size - header)) ?
|
||
|
len_remain : (ar->bmi.max_data_size - header);
|
||
|
|
||
|
offset = 0;
|
||
|
endianBuf32 = cpu_to_le32(cid);
|
||
|
memcpy(&(ar->bmi.cmd_buf[offset]), &endianBuf32,
|
||
|
sizeof(endianBuf32));
|
||
|
offset += sizeof(cid);
|
||
|
endianBuf32 = cpu_to_le32(tx_len);
|
||
|
memcpy(&(ar->bmi.cmd_buf[offset]), &endianBuf32,
|
||
|
sizeof(endianBuf32));
|
||
|
offset += sizeof(tx_len);
|
||
|
memcpy(&(ar->bmi.cmd_buf[offset]), &buf[len - len_remain],
|
||
|
tx_len);
|
||
|
offset += tx_len;
|
||
|
|
||
|
ret = ath6kl_hif_bmi_write(ar, ar->bmi.cmd_buf, offset);
|
||
|
if (ret) {
|
||
|
ath6kl_err("Unable to write to the device: %d\n",
|
||
|
ret);
|
||
|
return ret;
|
||
|
}
|
||
|
|
||
|
len_remain -= tx_len;
|
||
|
}
|
||
|
|
||
|
return 0;
|
||
|
}
|
||
|
|
||
|
int ath6kl_bmi_lz_stream_start(struct ath6kl *ar, u32 addr)
|
||
|
{
|
||
|
u32 cid = BMI_LZ_STREAM_START;
|
||
|
int ret;
|
||
|
u32 offset;
|
||
|
u16 size;
|
||
|
u32 endianBuf32;
|
||
|
|
||
|
if (ar->bmi.done_sent) {
|
||
|
ath6kl_err("bmi done sent already, cmd %d disallowed\n", cid);
|
||
|
return -EACCES;
|
||
|
}
|
||
|
|
||
|
size = sizeof(cid) + sizeof(addr);
|
||
|
if (size > ar->bmi.max_cmd_size) {
|
||
|
WARN_ON(1);
|
||
|
return -EINVAL;
|
||
|
}
|
||
|
memset(ar->bmi.cmd_buf, 0, size);
|
||
|
|
||
|
ath6kl_dbg(ATH6KL_DBG_BMI,
|
||
|
"bmi LZ stream start: addr: 0x%x)\n",
|
||
|
addr);
|
||
|
|
||
|
offset = 0;
|
||
|
endianBuf32 = cpu_to_le32(cid);
|
||
|
memcpy(&(ar->bmi.cmd_buf[offset]), &endianBuf32, sizeof(endianBuf32));
|
||
|
offset += sizeof(cid);
|
||
|
endianBuf32 = cpu_to_le32(addr);
|
||
|
memcpy(&(ar->bmi.cmd_buf[offset]), &endianBuf32, sizeof(endianBuf32));
|
||
|
offset += sizeof(addr);
|
||
|
|
||
|
ret = ath6kl_hif_bmi_write(ar, ar->bmi.cmd_buf, offset);
|
||
|
if (ret) {
|
||
|
ath6kl_err("Unable to start LZ stream to the device: %d\n",
|
||
|
ret);
|
||
|
return ret;
|
||
|
}
|
||
|
|
||
|
return 0;
|
||
|
}
|
||
|
|
||
|
int ath6kl_bmi_fast_download(struct ath6kl *ar, u32 addr, u8 *buf, u32 len)
|
||
|
{
|
||
|
int ret;
|
||
|
u32 last_word = 0;
|
||
|
u32 last_word_offset = len & ~0x3;
|
||
|
u32 unaligned_bytes = len & 0x3;
|
||
|
|
||
|
ret = ath6kl_bmi_lz_stream_start(ar, addr);
|
||
|
if (ret)
|
||
|
return ret;
|
||
|
|
||
|
if (unaligned_bytes) {
|
||
|
/* copy the last word into a zero padded buffer */
|
||
|
memcpy(&last_word, &buf[last_word_offset], unaligned_bytes);
|
||
|
}
|
||
|
|
||
|
ret = ath6kl_bmi_lz_data(ar, buf, last_word_offset);
|
||
|
if (ret)
|
||
|
return ret;
|
||
|
|
||
|
if (unaligned_bytes)
|
||
|
ret = ath6kl_bmi_lz_data(ar, (u8 *)&last_word, 4);
|
||
|
|
||
|
if (!ret) {
|
||
|
/* Close compressed stream and open a new (fake) one.
|
||
|
* This serves mainly to flush Target caches. */
|
||
|
ret = ath6kl_bmi_lz_stream_start(ar, 0x00);
|
||
|
}
|
||
|
return ret;
|
||
|
}
|
||
|
|
||
|
void ath6kl_bmi_reset(struct ath6kl *ar)
|
||
|
{
|
||
|
ar->bmi.done_sent = false;
|
||
|
}
|
||
|
|
||
|
int ath6kl_bmi_init(struct ath6kl *ar)
|
||
|
{
|
||
|
if (WARN_ON(ar->bmi.max_data_size == 0))
|
||
|
return -EINVAL;
|
||
|
|
||
|
/* cmd + addr + len + data_size */
|
||
|
ar->bmi.max_cmd_size = ar->bmi.max_data_size + (sizeof(u32) * 3);
|
||
|
|
||
|
ar->bmi.cmd_buf = kzalloc(ar->bmi.max_cmd_size, GFP_ATOMIC);
|
||
|
if (!ar->bmi.cmd_buf)
|
||
|
return -ENOMEM;
|
||
|
|
||
|
return 0;
|
||
|
}
|
||
|
|
||
|
void ath6kl_bmi_cleanup(struct ath6kl *ar)
|
||
|
{
|
||
|
kfree(ar->bmi.cmd_buf);
|
||
|
ar->bmi.cmd_buf = NULL;
|
||
|
}
|