523 lines
12 KiB
C
523 lines
12 KiB
C
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/* Copyright (c) 2014-2015 The Linux Foundation. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met:
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* * Redistributions in binary form must reproduce the above
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* copyright notice, this list of conditions and the following
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* disclaimer in the documentation and/or other materials provided
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* with the distribution.
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* * Neither the name of The Linux Foundation nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
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* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
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* BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
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* OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
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* IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <debug.h>
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#include <platform/iomap.h>
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#include <platform/irqs.h>
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#include <platform/gpio.h>
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#include <reg.h>
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#include <target.h>
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#include <platform.h>
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#include <dload_util.h>
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#include <uart_dm.h>
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#include <mmc.h>
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#include <spmi.h>
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#include <board.h>
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#include <smem.h>
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#include <baseband.h>
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#include <regulator.h>
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#include <dev/keys.h>
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#include <pm8x41.h>
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#include <crypto5_wrapper.h>
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#include <clock.h>
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#include <partition_parser.h>
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#include <scm.h>
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#include <platform/clock.h>
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#include <platform/gpio.h>
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#include <platform/timer.h>
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#include <stdlib.h>
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#include <ufs.h>
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#include <boot_device.h>
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#include <qmp_phy.h>
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#include <sdhci_msm.h>
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#include <qusb2_phy.h>
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#include <rpmb.h>
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#include <rpm-glink.h>
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#if ENABLE_WBC
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#include <pm_app_smbchg.h>
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#endif
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#if LONG_PRESS_POWER_ON
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#include <shutdown_detect.h>
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#endif
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#if PON_VIB_SUPPORT
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#include <vibrator.h>
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#define VIBRATE_TIME 250
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#endif
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#define CE_INSTANCE 1
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#define CE_EE 0
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#define CE_FIFO_SIZE 64
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#define CE_READ_PIPE 3
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#define CE_WRITE_PIPE 2
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#define CE_READ_PIPE_LOCK_GRP 0
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#define CE_WRITE_PIPE_LOCK_GRP 0
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#define CE_ARRAY_SIZE 20
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#define PMIC_ARB_CHANNEL_NUM 0
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#define PMIC_ARB_OWNER_ID 0
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static void set_sdc_power_ctrl(void);
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static uint32_t mmc_pwrctl_base[] =
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{ MSM_SDC1_BASE, MSM_SDC2_BASE };
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static uint32_t mmc_sdhci_base[] =
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{ MSM_SDC1_SDHCI_BASE, MSM_SDC2_SDHCI_BASE };
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static uint32_t mmc_sdc_pwrctl_irq[] =
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{ SDCC1_PWRCTL_IRQ, SDCC2_PWRCTL_IRQ };
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struct mmc_device *dev;
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struct ufs_dev ufs_device;
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void target_early_init(void)
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{
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#if WITH_DEBUG_UART
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uart_dm_init(8, 0, BLSP2_UART1_BASE);
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#endif
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}
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/* Return 1 if vol_up pressed */
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int target_volume_up()
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{
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uint8_t status = 0;
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struct pm8x41_gpio gpio;
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/* Configure the GPIO */
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gpio.direction = PM_GPIO_DIR_IN;
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gpio.function = 0;
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gpio.pull = PM_GPIO_PULL_UP_30;
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gpio.vin_sel = 2;
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pm8x41_gpio_config(2, &gpio);
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/* Wait for the pmic gpio config to take effect */
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thread_sleep(1);
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/* Get status of P_GPIO_5 */
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pm8x41_gpio_get(2, &status);
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return !status; /* active low */
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}
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/* Return 1 if vol_down pressed */
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uint32_t target_volume_down()
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{
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return pm8x41_resin_status();
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}
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static void target_keystatus()
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{
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keys_init();
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if(target_volume_down())
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keys_post_event(KEY_VOLUMEDOWN, 1);
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if(target_volume_up())
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keys_post_event(KEY_VOLUMEUP, 1);
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}
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void target_uninit(void)
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{
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if (platform_boot_dev_isemmc())
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{
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mmc_put_card_to_sleep(dev);
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}
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if (is_sec_app_loaded())
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{
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if (unload_sec_app() < 0)
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{
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dprintf(CRITICAL, "Failed to unload App for rpmb\n");
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ASSERT(0);
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}
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}
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#if ENABLE_WBC
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if (board_hardware_id() == HW_PLATFORM_MTP)
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pm_appsbl_set_dcin_suspend(1);
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#endif
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if (crypto_initialized())
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{
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crypto_eng_cleanup();
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clock_ce_disable(CE_INSTANCE);
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}
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/* Tear down glink channels */
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rpm_glink_uninit();
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if (rpmb_uninit() < 0)
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{
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dprintf(CRITICAL, "RPMB uninit failed\n");
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ASSERT(0);
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}
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}
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static void set_sdc_power_ctrl()
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{
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/* Drive strength configs for sdc pins */
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struct tlmm_cfgs sdc1_hdrv_cfg[] =
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{
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{ SDC1_CLK_HDRV_CTL_OFF, TLMM_CUR_VAL_16MA, TLMM_HDRV_MASK, SDC1_HDRV_PULL_CTL },
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{ SDC1_CMD_HDRV_CTL_OFF, TLMM_CUR_VAL_10MA, TLMM_HDRV_MASK, SDC1_HDRV_PULL_CTL },
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{ SDC1_DATA_HDRV_CTL_OFF, TLMM_CUR_VAL_10MA, TLMM_HDRV_MASK, SDC1_HDRV_PULL_CTL },
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};
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/* Pull configs for sdc pins */
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struct tlmm_cfgs sdc1_pull_cfg[] =
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{
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{ SDC1_CLK_PULL_CTL_OFF, TLMM_NO_PULL, TLMM_PULL_MASK, SDC1_HDRV_PULL_CTL },
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{ SDC1_CMD_PULL_CTL_OFF, TLMM_PULL_UP, TLMM_PULL_MASK, SDC1_HDRV_PULL_CTL },
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{ SDC1_DATA_PULL_CTL_OFF, TLMM_PULL_UP, TLMM_PULL_MASK, SDC1_HDRV_PULL_CTL },
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};
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struct tlmm_cfgs sdc1_rclk_cfg[] =
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{
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{ SDC1_RCLK_PULL_CTL_OFF, TLMM_PULL_DOWN, TLMM_PULL_MASK, SDC1_HDRV_PULL_CTL },
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};
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/* Set the drive strength & pull control values */
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tlmm_set_hdrive_ctrl(sdc1_hdrv_cfg, ARRAY_SIZE(sdc1_hdrv_cfg));
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tlmm_set_pull_ctrl(sdc1_pull_cfg, ARRAY_SIZE(sdc1_pull_cfg));
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tlmm_set_pull_ctrl(sdc1_rclk_cfg, ARRAY_SIZE(sdc1_rclk_cfg));
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}
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uint32_t target_is_pwrkey_pon_reason()
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{
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uint8_t pon_reason = pm8950_get_pon_reason();
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if (pm8x41_get_is_cold_boot() && ((pon_reason == KPDPWR_N) || (pon_reason == (KPDPWR_N|PON1))))
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return 1;
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else
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return 0;
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}
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void target_sdc_init()
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{
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struct mmc_config_data config = {0};
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/* Set drive strength & pull ctrl values */
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set_sdc_power_ctrl();
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config.bus_width = DATA_BUS_WIDTH_8BIT;
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config.max_clk_rate = MMC_CLK_192MHZ;
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config.hs400_support = 1;
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/* Try slot 1*/
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config.slot = 1;
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config.sdhc_base = mmc_sdhci_base[config.slot - 1];
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config.pwrctl_base = mmc_pwrctl_base[config.slot - 1];
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config.pwr_irq = mmc_sdc_pwrctl_irq[config.slot - 1];
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if (!(dev = mmc_init(&config)))
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{
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/* Try slot 2 */
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config.slot = 2;
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config.max_clk_rate = MMC_CLK_200MHZ;
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config.sdhc_base = mmc_sdhci_base[config.slot - 1];
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config.pwrctl_base = mmc_pwrctl_base[config.slot - 1];
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config.pwr_irq = mmc_sdc_pwrctl_irq[config.slot - 1];
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if (!(dev = mmc_init(&config)))
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{
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dprintf(CRITICAL, "mmc init failed!");
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ASSERT(0);
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}
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}
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}
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void *target_mmc_device()
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{
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if (platform_boot_dev_isemmc())
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return (void *) dev;
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else
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return (void *) &ufs_device;
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}
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void target_init(void)
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{
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dprintf(INFO, "target_init()\n");
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pmic_info_populate();
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spmi_init(PMIC_ARB_CHANNEL_NUM, PMIC_ARB_OWNER_ID);
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/* Initialize Glink */
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rpm_glink_init();
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target_keystatus();
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#if defined(LONG_PRESS_POWER_ON) || defined(PON_VIB_SUPPORT)
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switch(board_hardware_id())
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{
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case HW_PLATFORM_QRD:
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#if LONG_PRESS_POWER_ON
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shutdown_detect();
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#endif
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#if PON_VIB_SUPPORT
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vib_timed_turn_on(VIBRATE_TIME);
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#endif
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break;
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}
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#endif
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if (target_use_signed_kernel())
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target_crypto_init_params();
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platform_read_boot_config();
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#ifdef MMC_SDHCI_SUPPORT
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if (platform_boot_dev_isemmc())
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{
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target_sdc_init();
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}
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#endif
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#ifdef UFS_SUPPORT
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if (!platform_boot_dev_isemmc())
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{
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ufs_device.base = UFS_BASE;
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ufs_init(&ufs_device);
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}
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#endif
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/* Storage initialization is complete, read the partition table info */
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mmc_read_partition_table(0);
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#if ENABLE_WBC
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/* Look for battery voltage and make sure we have enough to bootup
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* Otherwise initiate battery charging
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* Charging should happen as early as possible, any other driver
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* initialization before this should consider the power impact
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*/
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switch(board_hardware_id())
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{
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case HW_PLATFORM_MTP:
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case HW_PLATFORM_FLUID:
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pm_appsbl_chg_check_weak_battery_status(1);
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break;
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default:
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/* Charging not supported */
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break;
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};
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#endif
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if (rpmb_init() < 0)
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{
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dprintf(CRITICAL, "RPMB init failed\n");
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ASSERT(0);
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}
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}
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unsigned board_machtype(void)
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{
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return LINUX_MACHTYPE_UNKNOWN;
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}
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/* Detect the target type */
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void target_detect(struct board_data *board)
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{
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/* This is filled from board.c */
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}
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static uint8_t splash_override;
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/* Returns 1 if target supports continuous splash screen. */
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int target_cont_splash_screen()
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{
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uint8_t splash_screen = 0;
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if(!splash_override && !pm_appsbl_charging_in_progress()) {
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switch(board_hardware_id())
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{
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case HW_PLATFORM_SURF:
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case HW_PLATFORM_MTP:
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case HW_PLATFORM_FLUID:
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case HW_PLATFORM_QRD:
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dprintf(SPEW, "Target_cont_splash=1\n");
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splash_screen = 1;
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break;
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default:
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dprintf(SPEW, "Target_cont_splash=0\n");
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splash_screen = 0;
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}
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}
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return splash_screen;
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}
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void target_force_cont_splash_disable(uint8_t override)
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{
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splash_override = override;
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}
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/* Detect the modem type */
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void target_baseband_detect(struct board_data *board)
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{
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uint32_t platform;
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platform = board->platform;
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switch(platform) {
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case APQ8096:
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board->baseband = BASEBAND_APQ;
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break;
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case MSM8996:
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if (board->platform_version == 0x10000)
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board->baseband = BASEBAND_APQ;
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else
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board->baseband = BASEBAND_MSM;
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break;
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default:
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dprintf(CRITICAL, "Platform type: %u is not supported\n",platform);
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ASSERT(0);
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};
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}
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unsigned target_baseband()
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{
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return board_baseband();
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}
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void target_serialno(unsigned char *buf)
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{
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unsigned int serialno;
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if (target_is_emmc_boot()) {
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serialno = mmc_get_psn();
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snprintf((char *)buf, 13, "%x", serialno);
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}
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}
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int emmc_recovery_init(void)
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{
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return _emmc_recovery_init();
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}
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void target_usb_phy_reset()
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{
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usb30_qmp_phy_reset();
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qusb2_phy_reset();
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}
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target_usb_iface_t* target_usb30_init()
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{
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target_usb_iface_t *t_usb_iface;
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t_usb_iface = calloc(1, sizeof(target_usb_iface_t));
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ASSERT(t_usb_iface);
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t_usb_iface->phy_init = usb30_qmp_phy_init;
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t_usb_iface->phy_reset = target_usb_phy_reset;
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t_usb_iface->clock_init = clock_usb30_init;
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t_usb_iface->vbus_override = 1;
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return t_usb_iface;
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}
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/* identify the usb controller to be used for the target */
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const char * target_usb_controller()
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{
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return "dwc";
|
||
|
}
|
||
|
|
||
|
uint32_t target_override_pll()
|
||
|
{
|
||
|
if (board_soc_version() >= 0x20000)
|
||
|
return 0;
|
||
|
else
|
||
|
return 1;
|
||
|
}
|
||
|
|
||
|
crypto_engine_type board_ce_type(void)
|
||
|
{
|
||
|
return CRYPTO_ENGINE_TYPE_HW;
|
||
|
}
|
||
|
|
||
|
/* Set up params for h/w CE. */
|
||
|
void target_crypto_init_params()
|
||
|
{
|
||
|
struct crypto_init_params ce_params;
|
||
|
|
||
|
/* Set up base addresses and instance. */
|
||
|
ce_params.crypto_instance = CE_INSTANCE;
|
||
|
ce_params.crypto_base = MSM_CE_BASE;
|
||
|
ce_params.bam_base = MSM_CE_BAM_BASE;
|
||
|
|
||
|
/* Set up BAM config. */
|
||
|
ce_params.bam_ee = CE_EE;
|
||
|
ce_params.pipes.read_pipe = CE_READ_PIPE;
|
||
|
ce_params.pipes.write_pipe = CE_WRITE_PIPE;
|
||
|
ce_params.pipes.read_pipe_grp = CE_READ_PIPE_LOCK_GRP;
|
||
|
ce_params.pipes.write_pipe_grp = CE_WRITE_PIPE_LOCK_GRP;
|
||
|
|
||
|
/* Assign buffer sizes. */
|
||
|
ce_params.num_ce = CE_ARRAY_SIZE;
|
||
|
ce_params.read_fifo_size = CE_FIFO_SIZE;
|
||
|
ce_params.write_fifo_size = CE_FIFO_SIZE;
|
||
|
|
||
|
/* BAM is initialized by TZ for this platform.
|
||
|
* Do not do it again as the initialization address space
|
||
|
* is locked.
|
||
|
*/
|
||
|
ce_params.do_bam_init = 0;
|
||
|
|
||
|
crypto_init_params(&ce_params);
|
||
|
}
|
||
|
|
||
|
unsigned target_pause_for_battery_charge(void)
|
||
|
{
|
||
|
uint8_t pon_reason = pm8x41_get_pon_reason();
|
||
|
uint8_t is_cold_boot = pm8x41_get_is_cold_boot();
|
||
|
dprintf(INFO, "%s : pon_reason is %d cold_boot:%d\n", __func__,
|
||
|
pon_reason, is_cold_boot);
|
||
|
/* In case of fastboot reboot,adb reboot or if we see the power key
|
||
|
* pressed we do not want go into charger mode.
|
||
|
* fastboot reboot is warm boot with PON hard reset bit not set
|
||
|
* adb reboot is a cold boot with PON hard reset bit set
|
||
|
*/
|
||
|
if (is_cold_boot &&
|
||
|
(!(pon_reason & HARD_RST)) &&
|
||
|
(!(pon_reason & KPDPWR_N)) &&
|
||
|
((pon_reason & PON1)))
|
||
|
return 1;
|
||
|
else
|
||
|
return 0;
|
||
|
}
|
||
|
|
||
|
int set_download_mode(enum dload_mode mode)
|
||
|
{
|
||
|
int ret = 0;
|
||
|
ret = scm_dload_mode(mode);
|
||
|
|
||
|
return ret;
|
||
|
}
|
||
|
|
||
|
void pmic_reset_configure(uint8_t reset_type)
|
||
|
{
|
||
|
pm8994_reset_configure(reset_type);
|
||
|
}
|