451 lines
12 KiB
C
451 lines
12 KiB
C
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/* Copyright (c) 2013-2015, The Linux Foundation. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* * Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* * Neither the name of The Linux Foundation nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
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* OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#include <debug.h>
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#include <smem.h>
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#include <err.h>
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#include <msm_panel.h>
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#include <mipi_dsi.h>
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#include <pm8x41.h>
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#include <pm8x41_wled.h>
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#include <board.h>
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#include <mdp5.h>
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#include <scm.h>
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#include <platform/gpio.h>
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#include <platform/iomap.h>
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#include <target/display.h>
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#include "include/panel.h"
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#include "include/display_resource.h"
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#include "gcdb_display.h"
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#define HFPLL_LDO_ID 8
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static struct pm8x41_wled_data wled_ctrl = {
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.mod_scheme = 0x00,
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.led1_brightness = (0x0F << 8) | 0xEF,
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.max_duty_cycle = 0x01,
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.ovp = 0x0,
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.full_current_scale = 0x19,
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.fdbck = 0x1
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};
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static uint32_t dsi_pll_enable_seq_m(uint32_t pll_base)
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{
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uint32_t i = 0;
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uint32_t pll_locked = 0;
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mdss_dsi_uniphy_pll_sw_reset(pll_base);
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/*
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* Add hardware recommended delays between register writes for
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* the updates to take effect. These delays are necessary for the
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* PLL to successfully lock
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*/
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writel(0x01, pll_base + 0x0020); /* GLB CFG */
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udelay(200);
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writel(0x05, pll_base + 0x0020); /* GLB CFG */
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udelay(200);
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writel(0x0f, pll_base + 0x0020); /* GLB CFG */
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udelay(1000);
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mdss_dsi_uniphy_pll_lock_detect_setting(pll_base);
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pll_locked = readl(pll_base + 0x00c0) & 0x01;
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for (i = 0; (i < 4) && !pll_locked; i++) {
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writel(0x07, pll_base + 0x0020); /* GLB CFG */
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if (i != 0)
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writel(0x34, pll_base + 0x00070); /* CAL CFG1*/
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udelay(1);
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writel(0x0f, pll_base + 0x0020); /* GLB CFG */
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udelay(1000);
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mdss_dsi_uniphy_pll_lock_detect_setting(pll_base);
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pll_locked = readl(pll_base + 0x00c0) & 0x01;
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}
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return pll_locked;
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}
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static uint32_t dsi_pll_enable_seq_d(uint32_t pll_base)
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{
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uint32_t pll_locked = 0;
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mdss_dsi_uniphy_pll_sw_reset(pll_base);
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/*
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* Add hardware recommended delays between register writes for
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* the updates to take effect. These delays are necessary for the
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* PLL to successfully lock
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*/
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writel(0x01, pll_base + 0x0020); /* GLB CFG */
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udelay(200);
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writel(0x05, pll_base + 0x0020); /* GLB CFG */
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udelay(200);
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writel(0x07, pll_base + 0x0020); /* GLB CFG */
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udelay(200);
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writel(0x05, pll_base + 0x0020); /* GLB CFG */
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udelay(200);
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writel(0x07, pll_base + 0x0020); /* GLB CFG */
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udelay(200);
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writel(0x0f, pll_base + 0x0020); /* GLB CFG */
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udelay(1000);
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mdss_dsi_uniphy_pll_lock_detect_setting(pll_base);
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pll_locked = readl(pll_base + 0x00c0) & 0x01;
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return pll_locked;
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}
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static uint32_t dsi_pll_enable_seq_f1(uint32_t pll_base)
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{
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uint32_t pll_locked = 0;
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mdss_dsi_uniphy_pll_sw_reset(pll_base);
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/*
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* Add hardware recommended delays between register writes for
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* the updates to take effect. These delays are necessary for the
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* PLL to successfully lock
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*/
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writel(0x01, pll_base + 0x0020); /* GLB CFG */
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udelay(200);
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writel(0x05, pll_base + 0x0020); /* GLB CFG */
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udelay(200);
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writel(0x0f, pll_base + 0x0020); /* GLB CFG */
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udelay(200);
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writel(0x0d, pll_base + 0x0020); /* GLB CFG */
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udelay(200);
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writel(0x0f, pll_base + 0x0020); /* GLB CFG */
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udelay(1000);
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mdss_dsi_uniphy_pll_lock_detect_setting(pll_base);
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pll_locked = readl(pll_base + 0x00c0) & 0x01;
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return pll_locked;
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}
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static uint32_t dsi_pll_enable_seq_c(uint32_t pll_base)
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{
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uint32_t pll_locked = 0;
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mdss_dsi_uniphy_pll_sw_reset(pll_base);
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/*
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* Add hardware recommended delays between register writes for
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* the updates to take effect. These delays are necessary for the
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* PLL to successfully lock
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*/
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writel(0x01, pll_base + 0x0020); /* GLB CFG */
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udelay(200);
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writel(0x05, pll_base + 0x0020); /* GLB CFG */
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udelay(200);
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writel(0x0f, pll_base + 0x0020); /* GLB CFG */
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udelay(1000);
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mdss_dsi_uniphy_pll_lock_detect_setting(pll_base);
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pll_locked = readl(pll_base + 0x00c0) & 0x01;
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return pll_locked;
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}
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static uint32_t dsi_pll_enable_seq_e(uint32_t pll_base)
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{
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uint32_t pll_locked = 0;
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mdss_dsi_uniphy_pll_sw_reset(pll_base);
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/*
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* Add hardware recommended delays between register writes for
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* the updates to take effect. These delays are necessary for the
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* PLL to successfully lock
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*/
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writel(0x01, pll_base + 0x0020); /* GLB CFG */
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udelay(200);
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writel(0x05, pll_base + 0x0020); /* GLB CFG */
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udelay(200);
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writel(0x0d, pll_base + 0x0020); /* GLB CFG */
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udelay(1);
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writel(0x0f, pll_base + 0x0020); /* GLB CFG */
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udelay(1000);
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mdss_dsi_uniphy_pll_lock_detect_setting(pll_base);
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pll_locked = readl(pll_base + 0x00c0) & 0x01;
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return pll_locked;
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}
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static int msm8226_wled_backlight_ctrl(uint8_t enable)
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{
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if (enable) {
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pm8x41_wled_config(&wled_ctrl);
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pm8x41_wled_sink_control(enable);
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pm8x41_wled_iled_sync_control(enable);
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pm8x41_wled_led_mod_enable(enable);
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}
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pm8x41_wled_enable(enable);
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return NO_ERROR;
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}
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static int msm8226_pwm_backlight_ctrl(int gpio_num, int lpg_chan, int enable)
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{
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struct pm8x41_gpio gpio_param = {
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.direction = PM_GPIO_DIR_OUT,
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.function = PM_GPIO_FUNC_2,
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.vin_sel = 2, /* VIN_2 */
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.pull = PM_GPIO_PULL_UP_1_5 | PM_GPIO_PULLDOWN_10,
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.output_buffer = PM_GPIO_OUT_CMOS,
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.out_strength = PM_GPIO_OUT_DRIVE_HIGH,
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};
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dprintf(SPEW, "%s: gpio=%d lpg=%d enable=%d\n", __func__,
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gpio_num, lpg_chan, enable);
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if (enable) {
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pm8x41_gpio_config(gpio_num, &gpio_param);
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pm8x41_lpg_write(lpg_chan, 0x41, 0x33); /* LPG_PWM_SIZE_CLK, */
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pm8x41_lpg_write(lpg_chan, 0x42, 0x01); /* LPG_PWM_FREQ_PREDIV */
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pm8x41_lpg_write(lpg_chan, 0x43, 0x20); /* LPG_PWM_TYPE_CONFIG */
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pm8x41_lpg_write(lpg_chan, 0x44, 0xb2); /* LPG_VALUE_LSB */
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pm8x41_lpg_write(lpg_chan, 0x45, 0x01); /* LPG_VALUE_MSB */
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pm8x41_lpg_write(lpg_chan, 0x46, 0xe4); /* LPG_ENABLE_CONTROL */
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} else {
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pm8x41_lpg_write(lpg_chan, 0x46, 0x00);
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}
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return NO_ERROR;
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}
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int target_backlight_ctrl(struct backlight *bl, uint8_t enable)
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{
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uint32_t ret = NO_ERROR;
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dprintf(SPEW, "target_backlight_ctrl\n");
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if (!bl) {
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dprintf(CRITICAL, "backlight structure is not available\n");
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return ERR_INVALID_ARGS;
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}
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switch (bl->bl_interface_type) {
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case BL_WLED:
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ret = msm8226_wled_backlight_ctrl(enable);
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break;
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case BL_PWM:
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ret = msm8226_pwm_backlight_ctrl(pwm_gpio.pin_id,
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PWM_BL_LPG_CHAN_ID,
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enable);
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break;
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case BL_DCS:
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break;
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default:
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dprintf(CRITICAL, "backlight type:%d not supported\n",
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bl->bl_interface_type);
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return ERR_NOT_SUPPORTED;
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}
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return ret;
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}
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static void dsi_pll_enable_seq(uint32_t pll_base)
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{
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if (dsi_pll_enable_seq_m(pll_base)) {
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} else if (dsi_pll_enable_seq_d(pll_base)) {
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} else if (dsi_pll_enable_seq_d(pll_base)) {
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} else if (dsi_pll_enable_seq_f1(pll_base)) {
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} else if (dsi_pll_enable_seq_c(pll_base)) {
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} else if (dsi_pll_enable_seq_e(pll_base)) {
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} else {
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dprintf(CRITICAL, "Not able to enable the pll\n");
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}
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}
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int target_panel_clock(uint8_t enable, struct msm_panel_info *pinfo)
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{
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int32_t ret;
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struct mdss_dsi_pll_config *pll_data;
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dprintf(SPEW, "target_panel_clock\n");
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pll_data = pinfo->mipi.dsi_pll_config;
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if (enable) {
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mdp_gdsc_ctrl(enable);
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mmss_bus_clocks_enable();
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mdp_clock_enable();
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ret = restore_secure_cfg(SECURE_DEVICE_MDSS);
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if (ret) {
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dprintf(CRITICAL,
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"%s: Failed to restore MDP security configs",
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__func__);
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mdp_clock_disable();
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mmss_bus_clocks_disable();
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mdp_gdsc_ctrl(0);
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return ret;
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}
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mdss_dsi_auto_pll_config(pinfo->mipi.pll_base,
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pinfo->mipi.ctl_base, pll_data);
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dsi_pll_enable_seq(pinfo->mipi.pll_base);
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mmss_dsi_clocks_enable(pll_data->pclk_m,
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pll_data->pclk_n,
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pll_data->pclk_d);
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} else if(!target_cont_splash_screen()) {
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mmss_dsi_clocks_disable();
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mdp_clock_disable();
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mmss_bus_clocks_disable();
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mdp_gdsc_ctrl(enable);
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}
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return 0;
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}
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int target_panel_reset(uint8_t enable, struct panel_reset_sequence *resetseq,
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struct msm_panel_info *pinfo)
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{
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int ret = NO_ERROR;
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if (enable) {
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if (pinfo->mipi.use_enable_gpio) {
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gpio_tlmm_config(enable_gpio.pin_id, 0,
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enable_gpio.pin_direction, enable_gpio.pin_pull,
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enable_gpio.pin_strength,
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enable_gpio.pin_state);
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gpio_set_dir(enable_gpio.pin_id, 2);
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}
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gpio_tlmm_config(reset_gpio.pin_id, 0,
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reset_gpio.pin_direction, reset_gpio.pin_pull,
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reset_gpio.pin_strength, reset_gpio.pin_state);
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gpio_set_dir(reset_gpio.pin_id, 2);
|
||
|
|
|
||
|
|
gpio_set_value(reset_gpio.pin_id, resetseq->pin_state[0]);
|
||
|
|
mdelay(resetseq->sleep[0]);
|
||
|
|
gpio_set_value(reset_gpio.pin_id, resetseq->pin_state[1]);
|
||
|
|
mdelay(resetseq->sleep[1]);
|
||
|
|
gpio_set_value(reset_gpio.pin_id, resetseq->pin_state[2]);
|
||
|
|
mdelay(resetseq->sleep[2]);
|
||
|
|
} else if(!target_cont_splash_screen()) {
|
||
|
|
gpio_set_value(reset_gpio.pin_id, 0);
|
||
|
|
if (pinfo->mipi.use_enable_gpio)
|
||
|
|
gpio_set_value(enable_gpio.pin_id, 0);
|
||
|
|
}
|
||
|
|
|
||
|
|
return ret;
|
||
|
|
}
|
||
|
|
|
||
|
|
int target_ldo_ctrl(uint8_t enable, struct msm_panel_info *pinfo)
|
||
|
|
{
|
||
|
|
uint32_t ret = NO_ERROR;
|
||
|
|
uint32_t ldocounter = 0;
|
||
|
|
uint32_t pm8x41_ldo_base = 0x13F00;
|
||
|
|
|
||
|
|
while (ldocounter < TOTAL_LDO_DEFINED) {
|
||
|
|
struct pm8x41_ldo ldo_entry = LDO((pm8x41_ldo_base +
|
||
|
|
0x100 * ldo_entry_array[ldocounter].ldo_id),
|
||
|
|
ldo_entry_array[ldocounter].ldo_type);
|
||
|
|
|
||
|
|
dprintf(SPEW, "Setting %s\n",
|
||
|
|
ldo_entry_array[ldocounter].ldo_id);
|
||
|
|
|
||
|
|
/* Set voltage during power on */
|
||
|
|
if (enable) {
|
||
|
|
pm8x41_ldo_set_voltage(&ldo_entry,
|
||
|
|
ldo_entry_array[ldocounter].ldo_voltage);
|
||
|
|
|
||
|
|
pm8x41_ldo_control(&ldo_entry, enable);
|
||
|
|
|
||
|
|
} else if(!target_cont_splash_screen() &&
|
||
|
|
ldo_entry_array[ldocounter].ldo_id != HFPLL_LDO_ID) {
|
||
|
|
pm8x41_ldo_control(&ldo_entry, enable);
|
||
|
|
}
|
||
|
|
ldocounter++;
|
||
|
|
}
|
||
|
|
|
||
|
|
return ret;
|
||
|
|
}
|
||
|
|
|
||
|
|
int target_dsi_phy_config(struct mdss_dsi_phy_ctrl *phy_db)
|
||
|
|
{
|
||
|
|
memcpy(phy_db->regulator, panel_regulator_settings, REGULATOR_SIZE);
|
||
|
|
memcpy(phy_db->ctrl, panel_physical_ctrl, PHYSICAL_SIZE);
|
||
|
|
memcpy(phy_db->strength, panel_strength_ctrl, STRENGTH_SIZE);
|
||
|
|
memcpy(phy_db->bistCtrl, panel_bist_ctrl, BIST_SIZE);
|
||
|
|
memcpy(phy_db->laneCfg, panel_lane_config, LANE_SIZE);
|
||
|
|
return NO_ERROR;
|
||
|
|
}
|
||
|
|
|
||
|
|
bool target_display_panel_node(char *pbuf, uint16_t buf_size)
|
||
|
|
{
|
||
|
|
return gcdb_display_cmdline_arg(pbuf, buf_size);
|
||
|
|
}
|
||
|
|
|
||
|
|
void target_display_init(const char *panel_name)
|
||
|
|
{
|
||
|
|
uint32_t panel_loop = 0;
|
||
|
|
uint32_t ret = 0;
|
||
|
|
uint32_t fb_addr = MIPI_FB_ADDR;
|
||
|
|
struct oem_panel_data oem;
|
||
|
|
|
||
|
|
set_panel_cmd_string(panel_name);
|
||
|
|
oem = mdss_dsi_get_oem_data();
|
||
|
|
|
||
|
|
if (!strcmp(oem.panel, NO_PANEL_CONFIG)
|
||
|
|
|| !strcmp(oem.panel, SIM_VIDEO_PANEL)
|
||
|
|
|| !strcmp(oem.panel, SIM_CMD_PANEL)
|
||
|
|
|| oem.skip) {
|
||
|
|
dprintf(INFO, "Selected panel: %s\nSkip panel configuration\n",
|
||
|
|
oem.panel);
|
||
|
|
return;
|
||
|
|
}
|
||
|
|
|
||
|
|
if (board_hardware_subtype() == HW_PLATFORM_SUBTYPE_QVGA)
|
||
|
|
fb_addr = MIPI_FB_ADDR_QVGA;
|
||
|
|
|
||
|
|
do {
|
||
|
|
target_force_cont_splash_disable(false);
|
||
|
|
ret = gcdb_display_init(oem.panel, MDP_REV_50, fb_addr);
|
||
|
|
if (!ret || ret == ERR_NOT_SUPPORTED) {
|
||
|
|
break;
|
||
|
|
} else {
|
||
|
|
target_force_cont_splash_disable(true);
|
||
|
|
msm_display_off();
|
||
|
|
}
|
||
|
|
} while (++panel_loop <= oem_panel_max_auto_detect_panels());
|
||
|
|
|
||
|
|
if (!oem.cont_splash) {
|
||
|
|
dprintf(INFO, "Forcing continuous splash disable\n");
|
||
|
|
target_force_cont_splash_disable(true);
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
void target_display_shutdown(void)
|
||
|
|
{
|
||
|
|
gcdb_display_shutdown();
|
||
|
|
}
|