294 lines
9.3 KiB
C
294 lines
9.3 KiB
C
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/* Copyright (c) 2015, The Linux Foundation. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met:
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* * Redistributions in binary form must reproduce the above
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* copyright notice, this list of conditions and the following
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* disclaimer in the documentation and/or other materials provided
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* with the distribution.
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* * Neither the name of The Linux Foundation nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
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* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
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* BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
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* OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
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* IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <debug.h>
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#include <reg.h>
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#include <platform/iomap.h>
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#include <qgic.h>
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#include <qtimer.h>
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#include <mmu.h>
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#include <arch/arm/mmu.h>
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#include <smem.h>
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#define MB (1024 *1024)
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#define MSM_IOMAP_SIZE ((MSM_IOMAP_END - MSM_IOMAP_BASE)/MB)
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#define A7_SS_SIZE ((A7_SS_END - A7_SS_BASE)/MB)
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/* LK memory */
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#define LK_MEMORY (MMU_MEMORY_TYPE_NORMAL_WRITE_THROUGH | \
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MMU_MEMORY_AP_READ_WRITE)
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/* Scratch memory - Strongly ordered, non-executable */
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#define SCRATCH_MEMORY (MMU_MEMORY_TYPE_NORMAL_WRITE_THROUGH | \
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MMU_MEMORY_AP_READ_WRITE | MMU_MEMORY_XN)
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/* Peripherals - shared device */
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#define IOMAP_MEMORY (MMU_MEMORY_TYPE_DEVICE_SHARED | \
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MMU_MEMORY_AP_READ_WRITE | MMU_MEMORY_XN)
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#define SCRATCH_REGION1_VIRT_START_128 0x88000000
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#define SCRATCH_REGION2_VIRT_START_128 (SCRATCH_REGION1_VIRT_START_128 + SCRATCH_REGION1_SIZE_128)
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static void ddr_based_mmu_mappings(mmu_section_t *table, uint32_t table_size);
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static uint64_t ddr_size;
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static void board_ddr_detect();
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/* Map all the accesssible memory according to the following rules:
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* 1. Map 1MB from MSM_SHARED_BASE with 1 -1 mapping.
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* 2. Map MEMBASE - MEMSIZE with 1 -1 mapping.
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* 3. Map all the scratch regions immediately after Appsbl memory.
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* Virtual addresses start right after Appsbl Virtual address.
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* 4. Map all the IOMAP space with 1 - 1 mapping.
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* 5. Map all the rest of the SDRAM/ IMEM regions as 1 -1.
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*/
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mmu_section_t mmu_section_table[] = {
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/* Physical addr, Virtual addr, Size (in MB), Flags */
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{MSM_SHARED_BASE, MSM_SHARED_BASE, 1, SCRATCH_MEMORY},
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{MEMBASE, MEMBASE, MEMSIZE / MB, LK_MEMORY},
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{MSM_IOMAP_BASE, MSM_IOMAP_BASE, MSM_IOMAP_SIZE, IOMAP_MEMORY},
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{A7_SS_BASE, A7_SS_BASE, A7_SS_SIZE, IOMAP_MEMORY},
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{MSM_SHARED_IMEM_BASE, MSM_SHARED_IMEM_BASE, 1, IOMAP_MEMORY},
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};
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mmu_section_t mmu_section_table_128[] = {
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{SCRATCH_REGION1_128, SCRATCH_REGION1_VIRT_START_128, SCRATCH_REGION1_SIZE_128/ MB, SCRATCH_MEMORY},
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{SCRATCH_REGION2_128, SCRATCH_REGION2_VIRT_START_128, SCRATCH_REGION2_SIZE_128/ MB, SCRATCH_MEMORY},
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};
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mmu_section_t mmu_section_table_256[] = {
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{SCRATCH_REGION_256, SCRATCH_REGION_256, SCRATCH_REGION_SIZE_256/ MB, SCRATCH_MEMORY},
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{KERNEL_REGION, KERNEL_REGION, KERNEL_REGION_SIZE/ MB, SCRATCH_MEMORY},
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};
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static void board_ddr_detect()
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{
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ddr_size = smem_get_ddr_size();
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/*128MB DDR*/
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if(ddr_size == 0x8000000)
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ddr_based_mmu_mappings(mmu_section_table_128, ARRAY_SIZE(mmu_section_table_128));
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else
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ddr_based_mmu_mappings(mmu_section_table_256, ARRAY_SIZE(mmu_section_table_256));
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}
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void platform_early_init(void)
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{
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board_init();
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platform_clock_init();
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qgic_init();
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qtimer_init();
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scm_init();
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board_ddr_detect();
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}
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void platform_init(void)
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{
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dprintf(INFO, "platform_init()\n");
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}
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void platform_uninit(void)
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{
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qtimer_uninit();
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qpic_nand_uninit();
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}
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uint32_t platform_get_sclk_count(void)
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{
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return readl(MPM2_MPM_SLEEP_TIMETICK_COUNT_VAL);
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}
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addr_t get_bs_info_addr()
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{
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return ((addr_t)BS_INFO_ADDR);
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}
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addr_t platform_get_virt_to_phys_mapping(addr_t virt_addr)
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{
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uint32_t paddr;
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uint32_t table_size = ARRAY_SIZE(mmu_section_table);
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uint32_t limit;
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for (uint32_t i = 0; i < table_size; i++)
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{
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limit = (mmu_section_table[i].num_of_sections * MB) - 0x1;
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if (virt_addr >= mmu_section_table[i].vaddress &&
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virt_addr <= (mmu_section_table[i].vaddress + limit))
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{
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paddr = mmu_section_table[i].paddress + (virt_addr - mmu_section_table[i].vaddress);
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return paddr;
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}
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}
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if(ddr_size == 0x8000000)
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{
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table_size = ARRAY_SIZE(mmu_section_table_128);
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for (uint32_t i = 0; i < table_size; i++)
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{
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limit = (mmu_section_table_128[i].num_of_sections * MB) - 0x1;
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if (virt_addr >= mmu_section_table_128[i].vaddress &&
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virt_addr <= (mmu_section_table_128[i].vaddress + limit))
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{
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paddr = mmu_section_table_128[i].paddress + (virt_addr - mmu_section_table_128[i].vaddress);
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return paddr;
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}
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}
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}
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else
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{
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/* Any DDR > 256MB would be mapped here & LK would use only first 256 MB */
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table_size = ARRAY_SIZE(mmu_section_table_256);
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for (uint32_t i = 0; i < table_size; i++)
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{
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limit = (mmu_section_table_256[i].num_of_sections * MB) - 0x1;
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if (virt_addr >= mmu_section_table_256[i].vaddress &&
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virt_addr <= (mmu_section_table_256[i].vaddress + limit))
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{
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paddr = mmu_section_table_256[i].paddress + (virt_addr - mmu_section_table_256[i].vaddress);
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return paddr;
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}
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}
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}
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/* No special mapping found.
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* Assume 1-1 mapping.
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*/
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paddr = virt_addr;
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return paddr;
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}
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addr_t platform_get_phys_to_virt_mapping(addr_t phys_addr)
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{
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uint32_t vaddr;
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uint32_t table_size = ARRAY_SIZE(mmu_section_table);
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uint32_t limit;
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for (uint32_t i = 0; i < table_size; i++)
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{
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limit = (mmu_section_table[i].num_of_sections * MB) - 0x1;
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if (phys_addr >= mmu_section_table[i].paddress &&
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phys_addr <= (mmu_section_table[i].paddress + limit))
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{
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vaddr = mmu_section_table[i].vaddress + (phys_addr - mmu_section_table[i].paddress);
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return vaddr;
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}
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}
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if(ddr_size == 0x8000000)
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{
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table_size = ARRAY_SIZE(mmu_section_table_128);
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for (uint32_t i = 0; i < table_size; i++)
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{
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limit = (mmu_section_table_128[i].num_of_sections * MB) - 0x1;
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if (phys_addr >= mmu_section_table_128[i].paddress &&
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phys_addr <= (mmu_section_table_128[i].paddress + limit))
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{
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vaddr = mmu_section_table_128[i].vaddress + (phys_addr - mmu_section_table_128[i].paddress);
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return vaddr;
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}
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}
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}
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else
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{
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/* Any DDR > 256MB would be mapped here & LK would use only first 256 MB */
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table_size = ARRAY_SIZE(mmu_section_table_256);
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for (uint32_t i = 0; i < table_size; i++)
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{
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limit = (mmu_section_table_256[i].num_of_sections * MB) - 0x1;
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if (phys_addr >= mmu_section_table_256[i].paddress &&
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phys_addr <= (mmu_section_table_256[i].paddress + limit))
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{
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vaddr = mmu_section_table_256[i].vaddress + (phys_addr - mmu_section_table_256[i].paddress);
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return vaddr;
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}
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}
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}
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/* No special mapping found.
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* Assume 1-1 mapping.
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*/
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vaddr = phys_addr;
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return vaddr;
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}
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/* Setup memory for this platform */
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void platform_init_mmu_mappings(void)
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{
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uint32_t i;
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uint32_t sections;
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uint32_t table_size = ARRAY_SIZE(mmu_section_table);
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/* Configure the MMU page entries for memory read from the
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mmu_section_table */
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for (i = 0; i < table_size; i++)
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{
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sections = mmu_section_table[i].num_of_sections;
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while (sections--)
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{
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arm_mmu_map_section(mmu_section_table[i].paddress +
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sections * MB,
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mmu_section_table[i].vaddress +
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sections * MB,
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mmu_section_table[i].flags);
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}
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}
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}
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/* Setup memory for this platform */
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static void ddr_based_mmu_mappings(mmu_section_t *table,uint32_t table_size)
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{
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uint32_t i;
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uint32_t sections;
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/* Configure the MMU page entries for memory read from the
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mmu_section_table */
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for (i = 0; i < table_size; i++)
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{
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sections = table->num_of_sections;
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while (sections--)
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{
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arm_mmu_map_section(table->paddress +
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sections * MB,
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table->vaddress +
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sections * MB,
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table->flags);
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}
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table++;
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}
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}
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int platform_use_identity_mmu_mappings(void)
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{
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/* Use only the mappings specified in this file. */
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return 0;
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}
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