357 lines
17 KiB
C
357 lines
17 KiB
C
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//------------------------------------------------------------------------------
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// ISC License (ISC)
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//
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// Copyright (c) 2004-2010, The Linux Foundation
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// All rights reserved.
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// Software was previously licensed under ISC license by Qualcomm Atheros, Inc.
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//
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//
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// Permission to use, copy, modify, and/or distribute this software for any
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// purpose with or without fee is hereby granted, provided that the above
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// copyright notice and this permission notice appear in all copies.
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//
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// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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//
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//
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//------------------------------------------------------------------------------
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//==============================================================================
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// Target register table macros and structure definitions
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//
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// Author(s): ="Atheros"
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//==============================================================================
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#ifndef TARGET_REG_TABLE_H_
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#define TARGET_REG_TABLE_H_
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#include "targaddrs.h"
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/*** WARNING : Add to the end of the TABLE! do not change the order ****/
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typedef struct targetdef_s {
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A_UINT32 d_RTC_SOC_BASE_ADDRESS;
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A_UINT32 d_RTC_WMAC_BASE_ADDRESS;
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A_UINT32 d_SYSTEM_SLEEP_OFFSET;
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A_UINT32 d_WLAN_SYSTEM_SLEEP_OFFSET;
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A_UINT32 d_WLAN_SYSTEM_SLEEP_DISABLE_LSB;
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A_UINT32 d_WLAN_SYSTEM_SLEEP_DISABLE_MASK;
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A_UINT32 d_CLOCK_CONTROL_OFFSET;
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A_UINT32 d_CLOCK_CONTROL_SI0_CLK_MASK;
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A_UINT32 d_RESET_CONTROL_OFFSET;
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A_UINT32 d_RESET_CONTROL_MBOX_RST_MASK;
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A_UINT32 d_RESET_CONTROL_SI0_RST_MASK;
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A_UINT32 d_WLAN_RESET_CONTROL_OFFSET;
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A_UINT32 d_WLAN_RESET_CONTROL_COLD_RST_MASK;
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A_UINT32 d_WLAN_RESET_CONTROL_WARM_RST_MASK;
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A_UINT32 d_GPIO_BASE_ADDRESS;
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A_UINT32 d_GPIO_PIN0_OFFSET;
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A_UINT32 d_GPIO_PIN1_OFFSET;
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A_UINT32 d_GPIO_PIN0_CONFIG_MASK;
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A_UINT32 d_GPIO_PIN1_CONFIG_MASK;
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A_UINT32 d_SI_CONFIG_BIDIR_OD_DATA_LSB;
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A_UINT32 d_SI_CONFIG_BIDIR_OD_DATA_MASK;
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A_UINT32 d_SI_CONFIG_I2C_LSB;
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A_UINT32 d_SI_CONFIG_I2C_MASK;
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A_UINT32 d_SI_CONFIG_POS_SAMPLE_LSB;
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A_UINT32 d_SI_CONFIG_POS_SAMPLE_MASK;
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A_UINT32 d_SI_CONFIG_INACTIVE_CLK_LSB;
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A_UINT32 d_SI_CONFIG_INACTIVE_CLK_MASK;
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A_UINT32 d_SI_CONFIG_INACTIVE_DATA_LSB;
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A_UINT32 d_SI_CONFIG_INACTIVE_DATA_MASK;
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A_UINT32 d_SI_CONFIG_DIVIDER_LSB;
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A_UINT32 d_SI_CONFIG_DIVIDER_MASK;
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A_UINT32 d_SI_BASE_ADDRESS;
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A_UINT32 d_SI_CONFIG_OFFSET;
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A_UINT32 d_SI_TX_DATA0_OFFSET;
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A_UINT32 d_SI_TX_DATA1_OFFSET;
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A_UINT32 d_SI_RX_DATA0_OFFSET;
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A_UINT32 d_SI_RX_DATA1_OFFSET;
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A_UINT32 d_SI_CS_OFFSET;
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A_UINT32 d_SI_CS_DONE_ERR_MASK;
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A_UINT32 d_SI_CS_DONE_INT_MASK;
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A_UINT32 d_SI_CS_START_LSB;
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A_UINT32 d_SI_CS_START_MASK;
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A_UINT32 d_SI_CS_RX_CNT_LSB;
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A_UINT32 d_SI_CS_RX_CNT_MASK;
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A_UINT32 d_SI_CS_TX_CNT_LSB;
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A_UINT32 d_SI_CS_TX_CNT_MASK;
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A_UINT32 d_BOARD_DATA_SZ;
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A_UINT32 d_BOARD_EXT_DATA_SZ;
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A_UINT32 d_MBOX_BASE_ADDRESS;
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A_UINT32 d_LOCAL_SCRATCH_OFFSET;
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A_UINT32 d_CPU_CLOCK_OFFSET;
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A_UINT32 d_LPO_CAL_OFFSET;
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A_UINT32 d_GPIO_PIN10_OFFSET;
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A_UINT32 d_GPIO_PIN11_OFFSET;
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A_UINT32 d_GPIO_PIN12_OFFSET;
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A_UINT32 d_GPIO_PIN13_OFFSET;
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A_UINT32 d_CLOCK_GPIO_OFFSET;
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A_UINT32 d_CPU_CLOCK_STANDARD_LSB;
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A_UINT32 d_CPU_CLOCK_STANDARD_MASK;
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A_UINT32 d_LPO_CAL_ENABLE_LSB;
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A_UINT32 d_LPO_CAL_ENABLE_MASK;
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A_UINT32 d_CLOCK_GPIO_BT_CLK_OUT_EN_LSB;
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A_UINT32 d_CLOCK_GPIO_BT_CLK_OUT_EN_MASK;
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A_UINT32 d_ANALOG_INTF_BASE_ADDRESS;
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A_UINT32 d_GPIO_PIN9_OFFSET;
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} TARGET_REGISTER_TABLE;
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#define ATH_UNSUPPORTED_REG_OFFSET 0xffffffff
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#define ATH_SUPPORTED_BY_TARGET(reg_offset) ((reg_offset) != ATH_UNSUPPORTED_REG_OFFSET)
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#define BOARD_DATA_SZ_MAX 2048
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#if defined(MY_TARGET_DEF) /* { */
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#if defined(ATHR_WIN_DEF)
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#define ATH_REG_TABLE_DIRECT_ASSIGN
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#endif
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/* Cross-platform compatibility */
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#if !defined(SOC_RESET_CONTROL_OFFSET) && defined(RESET_CONTROL_OFFSET)
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#define SOC_RESET_CONTROL_OFFSET RESET_CONTROL_OFFSET
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#endif
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#if !defined(CLOCK_GPIO_OFFSET)
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#define CLOCK_GPIO_OFFSET ATH_UNSUPPORTED_REG_OFFSET
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#define CLOCK_GPIO_BT_CLK_OUT_EN_LSB 0
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#define CLOCK_GPIO_BT_CLK_OUT_EN_MASK 0
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#endif
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#ifdef ATH_REG_TABLE_DIRECT_ASSIGN
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static struct targetdef_s my_target_def = {
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RTC_SOC_BASE_ADDRESS,
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RTC_WMAC_BASE_ADDRESS,
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SYSTEM_SLEEP_OFFSET,
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WLAN_SYSTEM_SLEEP_OFFSET,
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WLAN_SYSTEM_SLEEP_DISABLE_LSB,
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WLAN_SYSTEM_SLEEP_DISABLE_MASK,
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CLOCK_CONTROL_OFFSET,
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CLOCK_CONTROL_SI0_CLK_MASK,
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SOC_RESET_CONTROL_OFFSET,
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RESET_CONTROL_MBOX_RST_MASK,
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RESET_CONTROL_SI0_RST_MASK,
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WLAN_RESET_CONTROL_OFFSET,
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WLAN_RESET_CONTROL_COLD_RST_MASK,
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WLAN_RESET_CONTROL_WARM_RST_MASK,
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GPIO_BASE_ADDRESS,
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GPIO_PIN0_OFFSET,
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GPIO_PIN1_OFFSET,
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GPIO_PIN0_CONFIG_MASK,
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GPIO_PIN1_CONFIG_MASK,
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SI_CONFIG_BIDIR_OD_DATA_LSB,
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SI_CONFIG_BIDIR_OD_DATA_MASK,
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SI_CONFIG_I2C_LSB,
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SI_CONFIG_I2C_MASK,
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SI_CONFIG_POS_SAMPLE_LSB,
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SI_CONFIG_POS_SAMPLE_MASK,
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SI_CONFIG_INACTIVE_CLK_LSB,
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SI_CONFIG_INACTIVE_CLK_MASK,
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SI_CONFIG_INACTIVE_DATA_LSB,
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SI_CONFIG_INACTIVE_DATA_MASK,
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SI_CONFIG_DIVIDER_LSB,
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SI_CONFIG_DIVIDER_MASK,
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SI_BASE_ADDRESS,
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SI_CONFIG_OFFSET,
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SI_TX_DATA0_OFFSET,
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SI_TX_DATA1_OFFSET,
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SI_RX_DATA0_OFFSET,
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SI_RX_DATA1_OFFSET,
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SI_CS_OFFSET,
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SI_CS_DONE_ERR_MASK,
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SI_CS_DONE_INT_MASK,
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SI_CS_START_LSB,
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SI_CS_START_MASK,
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SI_CS_RX_CNT_LSB,
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SI_CS_RX_CNT_MASK,
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SI_CS_TX_CNT_LSB,
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SI_CS_TX_CNT_MASK,
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MY_TARGET_BOARD_DATA_SZ,
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MY_TARGET_BOARD_EXT_DATA_SZ,
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MBOX_BASE_ADDRESS,
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LOCAL_SCRATCH_OFFSET,
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CPU_CLOCK_OFFSET,
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LPO_CAL_OFFSET,
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GPIO_PIN10_OFFSET,
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GPIO_PIN11_OFFSET,
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GPIO_PIN12_OFFSET,
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GPIO_PIN13_OFFSET,
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CLOCK_GPIO_OFFSET,
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CPU_CLOCK_STANDARD_LSB,
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CPU_CLOCK_STANDARD_MASK,
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LPO_CAL_ENABLE_LSB,
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LPO_CAL_ENABLE_MASK,
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CLOCK_GPIO_BT_CLK_OUT_EN_LSB,
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CLOCK_GPIO_BT_CLK_OUT_EN_MASK,
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ANALOG_INTF_BASE_ADDRESS,
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GPIO_PIN9_OFFSET,
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};
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#else
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static struct targetdef_s my_target_def = {
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.d_RTC_SOC_BASE_ADDRESS = RTC_SOC_BASE_ADDRESS,
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.d_RTC_WMAC_BASE_ADDRESS = RTC_WMAC_BASE_ADDRESS,
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.d_SYSTEM_SLEEP_OFFSET = WLAN_SYSTEM_SLEEP_OFFSET,
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.d_WLAN_SYSTEM_SLEEP_OFFSET = WLAN_SYSTEM_SLEEP_OFFSET,
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.d_WLAN_SYSTEM_SLEEP_DISABLE_LSB = WLAN_SYSTEM_SLEEP_DISABLE_LSB,
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.d_WLAN_SYSTEM_SLEEP_DISABLE_MASK = WLAN_SYSTEM_SLEEP_DISABLE_MASK,
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.d_CLOCK_CONTROL_OFFSET = CLOCK_CONTROL_OFFSET,
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.d_CLOCK_CONTROL_SI0_CLK_MASK = CLOCK_CONTROL_SI0_CLK_MASK,
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.d_RESET_CONTROL_OFFSET = SOC_RESET_CONTROL_OFFSET,
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.d_RESET_CONTROL_MBOX_RST_MASK = RESET_CONTROL_MBOX_RST_MASK,
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.d_RESET_CONTROL_SI0_RST_MASK = RESET_CONTROL_SI0_RST_MASK,
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.d_WLAN_RESET_CONTROL_OFFSET = WLAN_RESET_CONTROL_OFFSET,
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.d_WLAN_RESET_CONTROL_COLD_RST_MASK = WLAN_RESET_CONTROL_COLD_RST_MASK,
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.d_WLAN_RESET_CONTROL_WARM_RST_MASK = WLAN_RESET_CONTROL_WARM_RST_MASK,
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.d_GPIO_BASE_ADDRESS = GPIO_BASE_ADDRESS,
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.d_GPIO_PIN0_OFFSET = GPIO_PIN0_OFFSET,
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.d_GPIO_PIN1_OFFSET = GPIO_PIN1_OFFSET,
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.d_GPIO_PIN0_CONFIG_MASK = GPIO_PIN0_CONFIG_MASK,
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.d_GPIO_PIN1_CONFIG_MASK = GPIO_PIN1_CONFIG_MASK,
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.d_SI_CONFIG_BIDIR_OD_DATA_LSB = SI_CONFIG_BIDIR_OD_DATA_LSB,
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.d_SI_CONFIG_BIDIR_OD_DATA_MASK = SI_CONFIG_BIDIR_OD_DATA_MASK,
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.d_SI_CONFIG_I2C_LSB = SI_CONFIG_I2C_LSB,
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.d_SI_CONFIG_I2C_MASK = SI_CONFIG_I2C_MASK,
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.d_SI_CONFIG_POS_SAMPLE_LSB = SI_CONFIG_POS_SAMPLE_LSB,
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.d_SI_CONFIG_POS_SAMPLE_MASK = SI_CONFIG_POS_SAMPLE_MASK,
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.d_SI_CONFIG_INACTIVE_CLK_LSB = SI_CONFIG_INACTIVE_CLK_LSB,
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.d_SI_CONFIG_INACTIVE_CLK_MASK = SI_CONFIG_INACTIVE_CLK_MASK,
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.d_SI_CONFIG_INACTIVE_DATA_LSB = SI_CONFIG_INACTIVE_DATA_LSB,
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.d_SI_CONFIG_INACTIVE_DATA_MASK = SI_CONFIG_INACTIVE_DATA_MASK,
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.d_SI_CONFIG_DIVIDER_LSB = SI_CONFIG_DIVIDER_LSB,
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.d_SI_CONFIG_DIVIDER_MASK = SI_CONFIG_DIVIDER_MASK,
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.d_SI_BASE_ADDRESS = SI_BASE_ADDRESS,
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.d_SI_CONFIG_OFFSET = SI_CONFIG_OFFSET,
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.d_SI_TX_DATA0_OFFSET = SI_TX_DATA0_OFFSET,
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.d_SI_TX_DATA1_OFFSET = SI_TX_DATA1_OFFSET,
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.d_SI_RX_DATA0_OFFSET = SI_RX_DATA0_OFFSET,
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.d_SI_RX_DATA1_OFFSET = SI_RX_DATA1_OFFSET,
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.d_SI_CS_OFFSET = SI_CS_OFFSET,
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.d_SI_CS_DONE_ERR_MASK = SI_CS_DONE_ERR_MASK,
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.d_SI_CS_DONE_INT_MASK = SI_CS_DONE_INT_MASK,
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.d_SI_CS_START_LSB = SI_CS_START_LSB,
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.d_SI_CS_START_MASK = SI_CS_START_MASK,
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.d_SI_CS_RX_CNT_LSB = SI_CS_RX_CNT_LSB,
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.d_SI_CS_RX_CNT_MASK = SI_CS_RX_CNT_MASK,
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.d_SI_CS_TX_CNT_LSB = SI_CS_TX_CNT_LSB,
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.d_SI_CS_TX_CNT_MASK = SI_CS_TX_CNT_MASK,
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.d_BOARD_DATA_SZ = MY_TARGET_BOARD_DATA_SZ,
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.d_BOARD_EXT_DATA_SZ = MY_TARGET_BOARD_EXT_DATA_SZ,
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.d_MBOX_BASE_ADDRESS = MBOX_BASE_ADDRESS,
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.d_LOCAL_SCRATCH_OFFSET = LOCAL_SCRATCH_OFFSET,
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.d_CPU_CLOCK_OFFSET = CPU_CLOCK_OFFSET,
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.d_LPO_CAL_OFFSET = LPO_CAL_OFFSET,
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.d_GPIO_PIN10_OFFSET = GPIO_PIN10_OFFSET,
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.d_GPIO_PIN11_OFFSET = GPIO_PIN11_OFFSET,
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.d_GPIO_PIN12_OFFSET = GPIO_PIN12_OFFSET,
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.d_GPIO_PIN13_OFFSET = GPIO_PIN13_OFFSET,
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.d_CLOCK_GPIO_OFFSET = CLOCK_GPIO_OFFSET,
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.d_CPU_CLOCK_STANDARD_LSB = CPU_CLOCK_STANDARD_LSB,
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.d_CPU_CLOCK_STANDARD_MASK = CPU_CLOCK_STANDARD_MASK,
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.d_LPO_CAL_ENABLE_LSB = LPO_CAL_ENABLE_LSB,
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.d_LPO_CAL_ENABLE_MASK = LPO_CAL_ENABLE_MASK,
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.d_CLOCK_GPIO_BT_CLK_OUT_EN_LSB = CLOCK_GPIO_BT_CLK_OUT_EN_LSB,
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.d_CLOCK_GPIO_BT_CLK_OUT_EN_MASK = CLOCK_GPIO_BT_CLK_OUT_EN_MASK,
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.d_ANALOG_INTF_BASE_ADDRESS = ANALOG_INTF_BASE_ADDRESS,
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.d_GPIO_PIN9_OFFSET = GPIO_PIN9_OFFSET,
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};
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#endif
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#if MY_TARGET_BOARD_DATA_SZ > BOARD_DATA_SZ_MAX
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#error "BOARD_DATA_SZ_MAX is too small"
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#endif
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struct targetdef_s *MY_TARGET_DEF = &my_target_def;
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#else /* } { */
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#define RTC_SOC_BASE_ADDRESS (targetdef->d_RTC_SOC_BASE_ADDRESS)
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#define RTC_WMAC_BASE_ADDRESS (targetdef->d_RTC_WMAC_BASE_ADDRESS)
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#define SYSTEM_SLEEP_OFFSET (targetdef->d_SYSTEM_SLEEP_OFFSET)
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#define WLAN_SYSTEM_SLEEP_OFFSET (targetdef->d_WLAN_SYSTEM_SLEEP_OFFSET)
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#define WLAN_SYSTEM_SLEEP_DISABLE_LSB (targetdef->d_WLAN_SYSTEM_SLEEP_DISABLE_LSB)
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#define WLAN_SYSTEM_SLEEP_DISABLE_MASK (targetdef->d_WLAN_SYSTEM_SLEEP_DISABLE_MASK)
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#define CLOCK_CONTROL_OFFSET (targetdef->d_CLOCK_CONTROL_OFFSET)
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#define CLOCK_CONTROL_SI0_CLK_MASK (targetdef->d_CLOCK_CONTROL_SI0_CLK_MASK)
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#define RESET_CONTROL_OFFSET (targetdef->d_RESET_CONTROL_OFFSET)
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#define RESET_CONTROL_MBOX_RST_MASK (targetdef->d_RESET_CONTROL_MBOX_RST_MASK)
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#define RESET_CONTROL_SI0_RST_MASK (targetdef->d_RESET_CONTROL_SI0_RST_MASK)
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#define WLAN_RESET_CONTROL_OFFSET (targetdef->d_WLAN_RESET_CONTROL_OFFSET)
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#define WLAN_RESET_CONTROL_COLD_RST_MASK (targetdef->d_WLAN_RESET_CONTROL_COLD_RST_MASK)
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#define WLAN_RESET_CONTROL_WARM_RST_MASK (targetdef->d_WLAN_RESET_CONTROL_WARM_RST_MASK)
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#define GPIO_BASE_ADDRESS (targetdef->d_GPIO_BASE_ADDRESS)
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#define GPIO_PIN0_OFFSET (targetdef->d_GPIO_PIN0_OFFSET)
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#define GPIO_PIN1_OFFSET (targetdef->d_GPIO_PIN1_OFFSET)
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#define GPIO_PIN0_CONFIG_MASK (targetdef->d_GPIO_PIN0_CONFIG_MASK)
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#define GPIO_PIN1_CONFIG_MASK (targetdef->d_GPIO_PIN1_CONFIG_MASK)
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#define SI_CONFIG_BIDIR_OD_DATA_LSB (targetdef->d_SI_CONFIG_BIDIR_OD_DATA_LSB)
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#define SI_CONFIG_BIDIR_OD_DATA_MASK (targetdef->d_SI_CONFIG_BIDIR_OD_DATA_MASK)
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#define SI_CONFIG_I2C_LSB (targetdef->d_SI_CONFIG_I2C_LSB)
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#define SI_CONFIG_I2C_MASK (targetdef->d_SI_CONFIG_I2C_MASK)
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#define SI_CONFIG_POS_SAMPLE_LSB (targetdef->d_SI_CONFIG_POS_SAMPLE_LSB)
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#define SI_CONFIG_POS_SAMPLE_MASK (targetdef->d_SI_CONFIG_POS_SAMPLE_MASK)
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#define SI_CONFIG_INACTIVE_CLK_LSB (targetdef->d_SI_CONFIG_INACTIVE_CLK_LSB)
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#define SI_CONFIG_INACTIVE_CLK_MASK (targetdef->d_SI_CONFIG_INACTIVE_CLK_MASK)
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#define SI_CONFIG_INACTIVE_DATA_LSB (targetdef->d_SI_CONFIG_INACTIVE_DATA_LSB)
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#define SI_CONFIG_INACTIVE_DATA_MASK (targetdef->d_SI_CONFIG_INACTIVE_DATA_MASK)
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#define SI_CONFIG_DIVIDER_LSB (targetdef->d_SI_CONFIG_DIVIDER_LSB)
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#define SI_CONFIG_DIVIDER_MASK (targetdef->d_SI_CONFIG_DIVIDER_MASK)
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#define SI_BASE_ADDRESS (targetdef->d_SI_BASE_ADDRESS)
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#define SI_CONFIG_OFFSET (targetdef->d_SI_CONFIG_OFFSET)
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#define SI_TX_DATA0_OFFSET (targetdef->d_SI_TX_DATA0_OFFSET)
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#define SI_TX_DATA1_OFFSET (targetdef->d_SI_TX_DATA1_OFFSET)
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#define SI_RX_DATA0_OFFSET (targetdef->d_SI_RX_DATA0_OFFSET)
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#define SI_RX_DATA1_OFFSET (targetdef->d_SI_RX_DATA1_OFFSET)
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#define SI_CS_OFFSET (targetdef->d_SI_CS_OFFSET)
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#define SI_CS_DONE_ERR_MASK (targetdef->d_SI_CS_DONE_ERR_MASK)
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#define SI_CS_DONE_INT_MASK (targetdef->d_SI_CS_DONE_INT_MASK)
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#define SI_CS_START_LSB (targetdef->d_SI_CS_START_LSB)
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#define SI_CS_START_MASK (targetdef->d_SI_CS_START_MASK)
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#define SI_CS_RX_CNT_LSB (targetdef->d_SI_CS_RX_CNT_LSB)
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#define SI_CS_RX_CNT_MASK (targetdef->d_SI_CS_RX_CNT_MASK)
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#define SI_CS_TX_CNT_LSB (targetdef->d_SI_CS_TX_CNT_LSB)
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#define SI_CS_TX_CNT_MASK (targetdef->d_SI_CS_TX_CNT_MASK)
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#define EEPROM_SZ (targetdef->d_BOARD_DATA_SZ)
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#define EEPROM_EXT_SZ (targetdef->d_BOARD_EXT_DATA_SZ)
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#define MBOX_BASE_ADDRESS (targetdef->d_MBOX_BASE_ADDRESS)
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#define LOCAL_SCRATCH_OFFSET (targetdef->d_LOCAL_SCRATCH_OFFSET)
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#define CPU_CLOCK_OFFSET (targetdef->d_CPU_CLOCK_OFFSET)
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#define LPO_CAL_OFFSET (targetdef->d_LPO_CAL_OFFSET)
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#define GPIO_PIN10_OFFSET (targetdef->d_GPIO_PIN10_OFFSET)
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#define GPIO_PIN11_OFFSET (targetdef->d_GPIO_PIN11_OFFSET)
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#define GPIO_PIN12_OFFSET (targetdef->d_GPIO_PIN12_OFFSET)
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#define GPIO_PIN13_OFFSET (targetdef->d_GPIO_PIN13_OFFSET)
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#define CLOCK_GPIO_OFFSET (targetdef->d_CLOCK_GPIO_OFFSET)
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#define CPU_CLOCK_STANDARD_LSB (targetdef->d_CPU_CLOCK_STANDARD_LSB)
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#define CPU_CLOCK_STANDARD_MASK (targetdef->d_CPU_CLOCK_STANDARD_MASK)
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#define LPO_CAL_ENABLE_LSB (targetdef->d_LPO_CAL_ENABLE_LSB)
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#define LPO_CAL_ENABLE_MASK (targetdef->d_LPO_CAL_ENABLE_MASK)
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#define CLOCK_GPIO_BT_CLK_OUT_EN_LSB (targetdef->d_CLOCK_GPIO_BT_CLK_OUT_EN_LSB)
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#define CLOCK_GPIO_BT_CLK_OUT_EN_MASK (targetdef->d_CLOCK_GPIO_BT_CLK_OUT_EN_MASK)
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#define ANALOG_INTF_BASE_ADDRESS (targetdef->d_ANALOG_INTF_BASE_ADDRESS)
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#define GPIO_PIN9_OFFSET (targetdef->d_GPIO_PIN9_OFFSET)
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/* SET macros */
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#define WLAN_SYSTEM_SLEEP_DISABLE_SET(x) (((x) << WLAN_SYSTEM_SLEEP_DISABLE_LSB) & WLAN_SYSTEM_SLEEP_DISABLE_MASK)
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#define SI_CONFIG_BIDIR_OD_DATA_SET(x) (((x) << SI_CONFIG_BIDIR_OD_DATA_LSB) & SI_CONFIG_BIDIR_OD_DATA_MASK)
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#define SI_CONFIG_I2C_SET(x) (((x) << SI_CONFIG_I2C_LSB) & SI_CONFIG_I2C_MASK)
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#define SI_CONFIG_POS_SAMPLE_SET(x) (((x) << SI_CONFIG_POS_SAMPLE_LSB) & SI_CONFIG_POS_SAMPLE_MASK)
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#define SI_CONFIG_INACTIVE_CLK_SET(x) (((x) << SI_CONFIG_INACTIVE_CLK_LSB) & SI_CONFIG_INACTIVE_CLK_MASK)
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#define SI_CONFIG_INACTIVE_DATA_SET(x) (((x) << SI_CONFIG_INACTIVE_DATA_LSB) & SI_CONFIG_INACTIVE_DATA_MASK)
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#define SI_CONFIG_DIVIDER_SET(x) (((x) << SI_CONFIG_DIVIDER_LSB) & SI_CONFIG_DIVIDER_MASK)
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#define SI_CS_START_SET(x) (((x) << SI_CS_START_LSB) & SI_CS_START_MASK)
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#define SI_CS_RX_CNT_SET(x) (((x) << SI_CS_RX_CNT_LSB) & SI_CS_RX_CNT_MASK)
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#define SI_CS_TX_CNT_SET(x) (((x) << SI_CS_TX_CNT_LSB) & SI_CS_TX_CNT_MASK)
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#define LPO_CAL_ENABLE_SET(x) (((x) << LPO_CAL_ENABLE_LSB) & LPO_CAL_ENABLE_MASK)
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#define CPU_CLOCK_STANDARD_SET(x) (((x) << CPU_CLOCK_STANDARD_LSB) & CPU_CLOCK_STANDARD_MASK)
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#define CLOCK_GPIO_BT_CLK_OUT_EN_SET(x) (((x) << CLOCK_GPIO_BT_CLK_OUT_EN_LSB) & CLOCK_GPIO_BT_CLK_OUT_EN_MASK)
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extern struct targetdef_s *targetdef;
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#endif /* } */
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#endif /*TARGET_REG_TABLE_H_*/
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