272 lines
8.4 KiB
C
272 lines
8.4 KiB
C
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/*
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* Copyright (C) 2010 The Android Open Source Project
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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#ifndef ANDROID_CUTILS_ATOMIC_ARM_H
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#define ANDROID_CUTILS_ATOMIC_ARM_H
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#include <stdint.h>
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#include <machine/cpu-features.h>
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extern inline void android_compiler_barrier(void)
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{
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__asm__ __volatile__ ("" : : : "memory");
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}
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#if ANDROID_SMP == 0
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extern inline void android_memory_barrier(void)
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{
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android_compiler_barrier();
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}
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#elif defined(__ARM_HAVE_DMB)
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extern inline void android_memory_barrier(void)
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{
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__asm__ __volatile__ ("dmb" : : : "memory");
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}
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#elif defined(__ARM_HAVE_LDREX_STREX)
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extern inline void android_memory_barrier(void)
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{
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__asm__ __volatile__ ("mcr p15, 0, %0, c7, c10, 5"
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: : "r" (0) : "memory");
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}
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#else
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extern inline void android_memory_barrier(void)
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{
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typedef void (kuser_memory_barrier)(void);
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(*(kuser_memory_barrier *)0xffff0fa0)();
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}
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#endif
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extern inline int32_t android_atomic_acquire_load(volatile const int32_t *ptr)
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{
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int32_t value = *ptr;
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android_memory_barrier();
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return value;
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}
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extern inline int32_t android_atomic_release_load(volatile const int32_t *ptr)
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{
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android_memory_barrier();
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return *ptr;
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}
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extern inline void android_atomic_acquire_store(int32_t value,
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volatile int32_t *ptr)
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{
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*ptr = value;
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android_memory_barrier();
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}
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extern inline void android_atomic_release_store(int32_t value,
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volatile int32_t *ptr)
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{
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android_memory_barrier();
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*ptr = value;
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}
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#if defined(__thumb__)
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extern int android_atomic_cas(int32_t old_value, int32_t new_value,
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volatile int32_t *ptr);
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#elif defined(__ARM_HAVE_LDREX_STREX)
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extern inline int android_atomic_cas(int32_t old_value, int32_t new_value,
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volatile int32_t *ptr)
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{
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int32_t prev, status;
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do {
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__asm__ __volatile__ ("ldrex %0, [%3]\n"
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"mov %1, #0\n"
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"teq %0, %4\n"
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"strexeq %1, %5, [%3]"
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: "=&r" (prev), "=&r" (status), "+m"(*ptr)
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: "r" (ptr), "Ir" (old_value), "r" (new_value)
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: "cc");
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} while (__builtin_expect(status != 0, 0));
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return prev != old_value;
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}
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#else
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extern inline int android_atomic_cas(int32_t old_value, int32_t new_value,
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volatile int32_t *ptr)
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{
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typedef int (kuser_cmpxchg)(int32_t, int32_t, volatile int32_t *);
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int32_t prev, status;
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prev = *ptr;
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do {
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status = (*(kuser_cmpxchg *)0xffff0fc0)(old_value, new_value, ptr);
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if (__builtin_expect(status == 0, 1))
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return 0;
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prev = *ptr;
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} while (prev == old_value);
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return 1;
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}
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#endif
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extern inline int android_atomic_acquire_cas(int32_t old_value,
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int32_t new_value,
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volatile int32_t *ptr)
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{
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int status = android_atomic_cas(old_value, new_value, ptr);
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android_memory_barrier();
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return status;
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}
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extern inline int android_atomic_release_cas(int32_t old_value,
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int32_t new_value,
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volatile int32_t *ptr)
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{
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android_memory_barrier();
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return android_atomic_cas(old_value, new_value, ptr);
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}
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#if defined(__thumb__)
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extern int32_t android_atomic_swap(int32_t new_value,
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volatile int32_t *ptr);
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#elif defined(__ARM_HAVE_LDREX_STREX)
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extern inline int32_t android_atomic_swap(int32_t new_value,
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volatile int32_t *ptr)
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{
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int32_t prev, status;
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do {
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__asm__ __volatile__ ("ldrex %0, [%3]\n"
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"strex %1, %4, [%3]"
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: "=&r" (prev), "=&r" (status), "+m" (*ptr)
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: "r" (ptr), "r" (new_value)
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: "cc");
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} while (__builtin_expect(status != 0, 0));
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android_memory_barrier();
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return prev;
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}
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#else
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extern inline int32_t android_atomic_swap(int32_t new_value,
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volatile int32_t *ptr)
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{
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int32_t prev;
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__asm__ __volatile__ ("swp %0, %2, [%3]"
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: "=&r" (prev), "+m" (*ptr)
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: "r" (new_value), "r" (ptr)
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: "cc");
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android_memory_barrier();
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return prev;
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}
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#endif
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#if defined(__thumb__)
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extern int32_t android_atomic_add(int32_t increment,
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volatile int32_t *ptr);
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#elif defined(__ARM_HAVE_LDREX_STREX)
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extern inline int32_t android_atomic_add(int32_t increment,
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volatile int32_t *ptr)
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{
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int32_t prev, tmp, status;
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android_memory_barrier();
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do {
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__asm__ __volatile__ ("ldrex %0, [%4]\n"
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"add %1, %0, %5\n"
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"strex %2, %1, [%4]"
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: "=&r" (prev), "=&r" (tmp),
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"=&r" (status), "+m" (*ptr)
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: "r" (ptr), "Ir" (increment)
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: "cc");
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} while (__builtin_expect(status != 0, 0));
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return prev;
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}
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#else
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extern inline int32_t android_atomic_add(int32_t increment,
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volatile int32_t *ptr)
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{
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int32_t prev, status;
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android_memory_barrier();
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do {
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prev = *ptr;
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status = android_atomic_cas(prev, prev + increment, ptr);
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} while (__builtin_expect(status != 0, 0));
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return prev;
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}
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#endif
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extern inline int32_t android_atomic_inc(volatile int32_t *addr)
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{
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return android_atomic_add(1, addr);
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}
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extern inline int32_t android_atomic_dec(volatile int32_t *addr)
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{
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return android_atomic_add(-1, addr);
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}
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#if defined(__thumb__)
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extern int32_t android_atomic_and(int32_t value, volatile int32_t *ptr);
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#elif defined(__ARM_HAVE_LDREX_STREX)
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extern inline int32_t android_atomic_and(int32_t value, volatile int32_t *ptr)
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{
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int32_t prev, tmp, status;
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android_memory_barrier();
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do {
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__asm__ __volatile__ ("ldrex %0, [%4]\n"
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"and %1, %0, %5\n"
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"strex %2, %1, [%4]"
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: "=&r" (prev), "=&r" (tmp),
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"=&r" (status), "+m" (*ptr)
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: "r" (ptr), "Ir" (value)
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: "cc");
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} while (__builtin_expect(status != 0, 0));
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return prev;
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}
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#else
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extern inline int32_t android_atomic_and(int32_t value, volatile int32_t *ptr)
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{
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int32_t prev, status;
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android_memory_barrier();
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do {
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prev = *ptr;
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status = android_atomic_cas(prev, prev & value, ptr);
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} while (__builtin_expect(status != 0, 0));
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return prev;
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}
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#endif
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#if defined(__thumb__)
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extern int32_t android_atomic_or(int32_t value, volatile int32_t *ptr);
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#elif defined(__ARM_HAVE_LDREX_STREX)
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extern inline int32_t android_atomic_or(int32_t value, volatile int32_t *ptr)
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{
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int32_t prev, tmp, status;
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android_memory_barrier();
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do {
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__asm__ __volatile__ ("ldrex %0, [%4]\n"
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"orr %1, %0, %5\n"
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"strex %2, %1, [%4]"
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: "=&r" (prev), "=&r" (tmp),
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"=&r" (status), "+m" (*ptr)
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: "r" (ptr), "Ir" (value)
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: "cc");
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} while (__builtin_expect(status != 0, 0));
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return prev;
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}
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#else
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extern inline int32_t android_atomic_or(int32_t value, volatile int32_t *ptr)
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{
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int32_t prev, status;
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android_memory_barrier();
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do {
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prev = *ptr;
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status = android_atomic_cas(prev, prev | value, ptr);
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} while (__builtin_expect(status != 0, 0));
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return prev;
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}
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#endif
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#endif /* ANDROID_CUTILS_ATOMIC_ARM_H */
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