120 lines
3.4 KiB
C
120 lines
3.4 KiB
C
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/* Copyright (c) 2012, The Linux Foundation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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* only version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*/
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#ifndef MDSS_EDP_H
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#define MDSS_EDP_H
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#include <linux/platform_device.h>
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#include <linux/regulator/consumer.h>
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#include <linux/clk.h>
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#include "mdss_panel.h"
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#define edp_read(offset) readl_relaxed((offset))
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#define edp_write(offset, data) writel_relaxed((data), (offset))
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struct display_timing_desc {
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u32 pclk;
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u32 h_addressable; /* addressable + boder = active */
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u32 h_border;
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u32 h_blank; /* fporch + bporch + sync_pulse = blank */
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u32 h_fporch;
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u32 h_sync_pulse;
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u32 v_addressable; /* addressable + boder = active */
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u32 v_border;
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u32 v_blank; /* fporch + bporch + sync_pulse = blank */
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u32 v_fporch;
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u32 v_sync_pulse;
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u32 width_mm;
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u32 height_mm;
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u32 interlaced;
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u32 stereo;
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u32 sync_type;
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u32 sync_separate;
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u32 vsync_pol;
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u32 hsync_pol;
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};
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struct edp_edid {
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char id_name[4];
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short id_product;
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char version;
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char revision;
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char video_digital;
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char color_depth; /* 6, 8, 10, 12 and 14 bits */
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char color_format; /* RGB 4:4:4, YCrCb 4:4:4, Ycrcb 4:2:2 */
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char dpm; /* display power management */
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char sync_digital; /* 1 = digital */
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char sync_separate; /* 1 = separate */
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char vsync_pol; /* 0 = negative, 1 = positive */
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char hsync_pol; /* 0 = negative, 1 = positive */
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char ext_block_cnt;
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struct display_timing_desc timing[4];
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};
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struct dpcd_cap {
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char max_lane_count;
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u32 max_link_clk; /* 162, 270 and 540 Mb, divided by 10 */
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};
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struct mdss_edp_drv_pdata {
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/* device driver */
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int (*on) (struct mdss_panel_data *pdata);
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int (*off) (struct mdss_panel_data *pdata);
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struct platform_device *pdev;
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/* edp specific */
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struct mdss_panel_data panel_data;
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unsigned char *edp_base;
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unsigned char *mmss_cc_base;
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struct edp_edid edid;
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struct dpcd_cap dpcd;
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/* regulators */
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struct regulator *vdda_vreg;
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/* clocks */
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struct clk *aux_clk;
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struct clk *pixel_clk;
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struct clk *ahb_clk;
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struct clk *link_clk;
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int clk_on;
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/* gpios */
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int gpio_panel_en;
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int gpio_panel_pwm;
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/* backlight */
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struct pwm_device *bl_pwm;
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int lpg_channel;
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int pwm_period;
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};
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void mdss_edp_phy_sw_reset(unsigned char *edp_base);
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void mdss_edp_pll_configure(unsigned char *edp_base, int rate);
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void mdss_edp_enable_lane_bist(unsigned char *edp_base, int lane, int enable);
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void mdss_edp_enable_mainlink(unsigned char *edp_base, int enable);
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void mdss_edp_hw_powerup(unsigned char *edp_base, int enable);
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void mdss_edp_clk_enable(struct mdss_edp_drv_pdata *edp_drv);
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void mdss_edp_clk_disable(struct mdss_edp_drv_pdata *edp_drv);
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int mdss_edp_clk_init(struct mdss_edp_drv_pdata *edp_drv);
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void mdss_edp_clk_deinit(struct mdss_edp_drv_pdata *edp_drv);
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void mdss_edp_prepare_clocks(struct mdss_edp_drv_pdata *edp_drv);
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void mdss_edp_unprepare_clocks(struct mdss_edp_drv_pdata *edp_drv);
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void mdss_edp_config_clk(unsigned char *edp_base, unsigned char *mmss_cc_base);
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void mdss_edp_unconfig_clk(unsigned char *edp_base,
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unsigned char *mmss_cc_base);
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void mdss_edp_phy_misc_cfg(unsigned char *edp_base);
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#endif /* MDSS_EDP_H */
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