314 lines
11 KiB
C
314 lines
11 KiB
C
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/*
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* Copyright (C) ST-Ericsson AP Pte Ltd 2010
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*
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* ISP1763 Linux OTG Controller driver : hal
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*
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* This program is free software; you can redistribute it and/or modify it under the terms of
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* the GNU General Public License as published by the Free Software Foundation; version
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* 2 of the License.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT ANY
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* WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
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* FOR A PARTICULAR PURPOSE. See the GNU General Public License for more
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* details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
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*
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* This is a hardware abstraction layer header file.
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*
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* Author : wired support <wired.support@stericsson.com>
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*
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*/
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#ifndef HAL_INTF_H
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#define HAL_INTF_H
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/* Specify package here instead of including package.h */
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/* #include "package.h" */
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#define HCD_PACKAGE
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#define NON_PCI
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//#define PXA300
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//#define MSEC_INT_BASED
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#ifdef MSEC_INT_BASED
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#define THREAD_BASED
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#endif
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#ifndef DATABUS_WIDTH_16
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#define DATABUS_WIDTH_16
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#endif
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#ifdef DATABUS_WIDTH_16
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/*DMA SUPPORT */
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/* #define ENABLE_PLX_DMA */
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//#undef ENABLE_PLX_DMA//PXA300
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#endif
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//#define EDGE_INTERRUPT
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//#define POL_HIGH_INTERRUPT
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#define DMA_BUF_SIZE (4096 * 2)
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#define ISP1763_CHIPID 0x176320
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/* Values for id_flags filed of isp1763_driver_t */
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#define ISP1763_HC 0 /* Host Controller Driver */
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#define ISP1763_DC 1 /* Device Controller Driver */
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#define ISP1763_OTG 2 /* Otg Controller Driver */
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#define ISP1763_LAST_DEV (ISP1763_OTG + 1)
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#define ISP1763_1ST_DEV (ISP1763_HC)
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#ifdef PXA300
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#define HC_SPARAMS_REG (0x04<<1) /* Structural Parameters Register */
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#define HC_CPARAMS_REG (0x08<<1) /* Capability Parameters Register */
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#define HC_USBCMD_REG (0x8C<<1) /* USB Command Register */
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#define HC_USBSTS_REG (0x90<<1) /* USB Status Register */
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#define HC_INTERRUPT_REG_EHCI (0x94<<1) /* INterrupt Enable Register */
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#define HC_FRINDEX_REG (0x98<<1) /* Frame Index Register */
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#define HC_CONFIGFLAG_REG (0x9C<<1) /* Conigured Flag Register */
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#define HC_PORTSC1_REG (0xA0<<1) /* Port Status Control for Port1 */
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/*ISO Transfer Registers */
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#define HC_ISO_PTD_DONEMAP_REG (0xA4<<1) /* ISO PTD Done Map Register */
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#define HC_ISO_PTD_SKIPMAP_REG (0xA6<<1) /* ISO PTD Skip Map Register */
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#define HC_ISO_PTD_LASTPTD_REG (0xA8<<1) /* ISO PTD Last PTD Register */
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/*INT Transfer Registers */
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#define HC_INT_PTD_DONEMAP_REG (0xAA<<1) /* INT PTD Done Map Register */
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#define HC_INT_PTD_SKIPMAP_REG (0xAC<<1) /* INT PTD Skip Map Register */
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#define HC_INT_PTD_LASTPTD_REG (0xAE<<1) /* INT PTD Last PTD Register */
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/*ATL Transfer Registers */
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#define HC_ATL_PTD_DONEMAP_REG (0xB0<<1) /* ATL PTD Last PTD Register */
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#define HC_ATL_PTD_SKIPMAP_REG (0xB2<<1) /* ATL PTD Last PTD Register */
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#define HC_ATL_PTD_LASTPTD_REG (0xB4<<1) /* ATL PTD Last PTD Register */
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/*General Purpose Registers */
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#define HC_HW_MODE_REG (0x0C<<1) /* H/W Mode Register */
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#define HC_CHIP_ID_REG (0x70<<1) /* Chip ID Register */
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#define HC_SCRATCH_REG (0x78<<1) /* Scratch Register */
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#define HC_RESET_REG (0xB8<<1) /* HC Reset Register */
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#define HC_HWMODECTRL_REG (0xB6<<1)
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#define HC_UNLOCK_DEVICE (0x7C<<1)
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/* Interrupt Registers */
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#define HC_INTERRUPT_REG (0xD4<<1) /* Interrupt Register */
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#define HC_INTENABLE_REG (0xD6<<1) /* Interrupt enable Register */
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#define HC_ISO_IRQ_MASK_OR_REG (0xD8<<1) /* ISO Mask OR Register */
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#define HC_INT_IRQ_MASK_OR_REG (0xDA<<1) /* INT Mask OR Register */
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#define HC_ATL_IRQ_MASK_OR_REG (0xDC<<1) /* ATL Mask OR Register */
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#define HC_ISO_IRQ_MASK_AND_REG (0xDE<<1) /* ISO Mask AND Register */
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#define HC_INT_IRQ_MASK_AND_REG (0xE0<<1) /* INT Mask AND Register */
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#define HC_ATL_IRQ_MASK_AND_REG (0xE2<<1) /* ATL Mask AND Register */
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/*power control reg */
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#define HC_POWER_DOWN_CONTROL_REG (0xD0<<1)
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/*RAM Registers */
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#define HC_DMACONFIG_REG (0xBC<<1) /* DMA Config Register */
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#define HC_MEM_READ_REG (0xC4<<1) /* Memory Register */
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#define HC_DATA_REG (0xC6<<1) /* Data Register */
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#define OTG_CTRL_SET_REG (0xE4<<1)
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#define OTG_CTRL_CLEAR_REG (0xE6<<1)
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#define OTG_SOURCE_REG (0xE8<<1)
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#define OTG_INTR_EN_F_SET_REG (0xF0<<1)
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#define OTG_INTR_EN_R_SET_REG (0xF4<<1) /* OTG Interrupt Enable Rise register */
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#else
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#define HC_SPARAMS_REG 0x04 /* Structural Parameters Register */
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#define HC_CPARAMS_REG 0x08 /* Capability Parameters Register */
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#define HC_USBCMD_REG 0x8C /* USB Command Register */
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#define HC_USBSTS_REG 0x90 /* USB Status Register */
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#define HC_INTERRUPT_REG_EHCI 0x94 /* INterrupt Enable Register */
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#define HC_FRINDEX_REG 0x98 /* Frame Index Register */
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#define HC_CONFIGFLAG_REG 0x9C /* Conigured Flag Register */
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#define HC_PORTSC1_REG 0xA0 /* Port Status Control for Port1 */
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/*ISO Transfer Registers */
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#define HC_ISO_PTD_DONEMAP_REG 0xA4 /* ISO PTD Done Map Register */
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#define HC_ISO_PTD_SKIPMAP_REG 0xA6 /* ISO PTD Skip Map Register */
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#define HC_ISO_PTD_LASTPTD_REG 0xA8 /* ISO PTD Last PTD Register */
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/*INT Transfer Registers */
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#define HC_INT_PTD_DONEMAP_REG 0xAA /* INT PTD Done Map Register */
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#define HC_INT_PTD_SKIPMAP_REG 0xAC /* INT PTD Skip Map Register */
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#define HC_INT_PTD_LASTPTD_REG 0xAE /* INT PTD Last PTD Register */
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/*ATL Transfer Registers */
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#define HC_ATL_PTD_DONEMAP_REG 0xB0 /* ATL PTD Last PTD Register */
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#define HC_ATL_PTD_SKIPMAP_REG 0xB2 /* ATL PTD Last PTD Register */
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#define HC_ATL_PTD_LASTPTD_REG 0xB4 /* ATL PTD Last PTD Register */
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/*General Purpose Registers */
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#define HC_HW_MODE_REG 0x0C //0xB6 /* H/W Mode Register */
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#define HC_CHIP_ID_REG 0x70 /* Chip ID Register */
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#define HC_SCRATCH_REG 0x78 /* Scratch Register */
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#define HC_RESET_REG 0xB8 /* HC Reset Register */
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#define HC_HWMODECTRL_REG 0xB6 //0x0C /* H/W Mode control Register */
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#define HC_UNLOCK_DEVICE 0x7C
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/* Interrupt Registers */
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#define HC_INTERRUPT_REG 0xD4 /* Interrupt Register */
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#define HC_INTENABLE_REG 0xD6 /* Interrupt enable Register */
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#define HC_ISO_IRQ_MASK_OR_REG 0xD8 /* ISO Mask OR Register */
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#define HC_INT_IRQ_MASK_OR_REG 0xDA /* INT Mask OR Register */
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#define HC_ATL_IRQ_MASK_OR_REG 0xDC /* ATL Mask OR Register */
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#define HC_ISO_IRQ_MASK_AND_REG 0xDE /* ISO Mask AND Register */
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#define HC_INT_IRQ_MASK_AND_REG 0xE0 /* INT Mask AND Register */
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#define HC_ATL_IRQ_MASK_AND_REG 0xE2 /* ATL Mask AND Register */
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/*power control reg */
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#define HC_POWER_DOWN_CONTROL_REG 0xD0
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/*RAM Registers */
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#define HC_DMACONFIG_REG 0xBC /* DMA Config Register */
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#define HC_MEM_READ_REG 0xC4 /* Memory Register */
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#define HC_DATA_REG 0xC6 /* Data Register */
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#define OTG_CTRL_SET_REG 0xE4
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#define OTG_CTRL_CLEAR_REG 0xE6
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#define OTG_SOURCE_REG 0xE8
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#define OTG_INTR_EN_F_SET_REG 0xF0 /* OTG Interrupt Enable Fall register */
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#define OTG_INTR_EN_R_SET_REG 0xF4 /* OTG Interrupt Enable Rise register */
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#endif
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#define OTG_CTRL_DPPULLUP 0x0001
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#define OTG_CTRL_DPPULLDOWN 0x0002
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#define OTG_CTRL_DMPULLDOWN 0x0004
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#define OTG_CTRL_VBUS_DRV 0x0010
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#define OTG_CTRL_VBUS_DISCHRG 0x0020
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#define OTG_CTRL_VBUS_CHRG 0x0040
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#define OTG_CTRL_SW_SEL_HC_DC 0x0080
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#define OTG_CTRL_BDIS_ACON_EN 0x0100
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#define OTG_CTRL_OTG_SE0_EN 0x0200
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#define OTG_CTRL_OTG_DISABLE 0x0400
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#define OTG_CTRL_VBUS_DRV_PORT2 0x1000
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#define OTG_CTRL_SW_SEL_HC_2 0x8000
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/*interrupt count and buffer status register*/
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#ifdef PXA300
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#define HC_BUFFER_STATUS_REG (0xBA<<1)
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#define HC_INT_THRESHOLD_REG (0xC8<<1)
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#else
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#define HC_BUFFER_STATUS_REG 0xBA
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#define HC_INT_THRESHOLD_REG 0xC8
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#endif
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#define HC_OTG_INTERRUPT 0x400
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#ifdef PXA300
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#define DC_CHIPID (0x70<<1)
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#else
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#define DC_CHIPID 0x70
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#endif
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#ifdef PXA300
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#define FPGA_CONFIG_REG (0x100<<1)
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#else
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#define FPGA_CONFIG_REG 0x100
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#endif
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#define HC_HW_MODE_GOBAL_INTR_ENABLE 0x01
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#define HC_HW_MODE_INTR_EDGE 0x02
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#define HC_HW_MODE_INTR_POLARITY_HIGH 0x04
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#define HC_HW_MODE_LOCK 0x08
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#define HC_HW_MODE_DATABUSWIDTH_8 0x10
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#define HC_HW_MODE_DREQ_POL_HIGH 0x20
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#define HC_HW_MODE_DACK_POL_HIGH 0x40
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#define HC_HW_MODE_COMN_INT 0x80
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struct isp1763_driver;
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typedef struct _isp1763_id {
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u16 idVendor;
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u16 idProduct;
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u32 driver_info;
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} isp1763_id;
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typedef struct isp1763_dev {
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/*added for pci device */
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#ifdef NON_PCI
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struct platform_device *dev;
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#else /*PCI*/
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struct pci_dev *pcidev;
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#endif
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struct isp1763_driver *driver; /* which driver has allocated this device */
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void *driver_data; /* data private to the host controller driver */
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void *otg_driver_data; /*data private for otg controler */
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unsigned char index; /* local controller (HC/DC/OTG) */
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unsigned int irq; /*Interrupt Channel allocated for this device */
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void (*handler) (struct isp1763_dev * dev, void *isr_data); /* Interrupt Serrvice Routine */
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void *isr_data; /* isr data of the driver */
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unsigned long int_reg; /* Interrupt register */
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unsigned long alt_int_reg; /* Interrupt register 2 */
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unsigned long start;
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unsigned long length;
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struct resource *mem_res;
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unsigned long io_base; /* Start Io address space for this device */
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unsigned long io_len; /* IO address space length for this device */
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unsigned long chip_id; /* Chip Id */
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char name[80]; /* device name */
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int active; /* device status */
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/* DMA resources should come here */
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unsigned long dma;
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u8 *baseaddress; /*base address for i/o ops */
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u8 *dmabase;
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isp1763_id *id;
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} isp1763_dev_t;
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typedef struct isp1763_driver {
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char *name;
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unsigned long index; /* HC or DC or OTG */
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isp1763_id *id; /*device ids */
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int (*probe) (struct isp1763_dev * dev, isp1763_id * id); /* New device inserted */
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void (*remove) (struct isp1763_dev * dev); /* Device removed (NULL if not a hot-plug capable driver) */
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void (*suspend) (struct isp1763_dev * dev); /* Device suspended */
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void (*resume) (struct isp1763_dev * dev); /* Device woken up */
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void (*remotewakeup) (struct isp1763_dev *dev); /* Remote Wakeup */
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void (*powerup) (struct isp1763_dev *dev); /* Device poweup mode */
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void (*powerdown) (struct isp1763_dev *dev); /* Device power down mode */
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} isp_1763_driver_t;
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struct usb_device *phci_register_otg_device(struct isp1763_dev *dev);
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/*otg exported function from host*/
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int phci_suspend_otg_port(struct isp1763_dev *dev, u32 command);
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int phci_enumerate_otg_port(struct isp1763_dev *dev, u32 command);
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extern int isp1763_register_driver(struct isp1763_driver *drv);
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extern void isp1763_unregister_driver(struct isp1763_driver *drv);
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extern int isp1763_request_irq(void (*handler)(struct isp1763_dev * dev, void *isr_data),
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struct isp1763_dev *dev, void *isr_data);
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extern void isp1763_free_irq(struct isp1763_dev *dev, void *isr_data);
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extern u32 isp1763_reg_read32(isp1763_dev_t * dev, u16 reg, u32 data);
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extern u16 isp1763_reg_read16(isp1763_dev_t * dev, u16 reg, u16 data);
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extern u8 isp1763_reg_read8(struct isp1763_dev *dev, u16 reg, u8 data);
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extern void isp1763_reg_write32(isp1763_dev_t * dev, u16 reg, u32 data);
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extern void isp1763_reg_write16(isp1763_dev_t * dev, u16 reg, u16 data);
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extern void isp1763_reg_write8(struct isp1763_dev *dev, u16 reg, u8 data);
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extern int isp1763_mem_read(isp1763_dev_t * dev, u32 start_add,
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u32 end_add, u32 * buffer, u32 length, u16 dir);
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extern int isp1763_mem_write(isp1763_dev_t * dev, u32 start_add,
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u32 end_add, u32 * buffer, u32 length, u16 dir);
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#endif /* __HAL_INTF_H__ */
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