574 lines
20 KiB
C
574 lines
20 KiB
C
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/* Copyright (c) 2008-2013, The Linux Foundation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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* only version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*/
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#ifndef _SPI_QSD_H
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#define _SPI_QSD_H
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#define SPI_DRV_NAME "spi_qsd"
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#if defined(CONFIG_SPI_QSD) || defined(CONFIG_SPI_QSD_MODULE)
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#define QSD_REG(x) (x)
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#define QUP_REG(x)
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#define SPI_FIFO_WORD_CNT 0x0048
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#else
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#define QSD_REG(x)
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#define QUP_REG(x) (x)
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#define QUP_CONFIG 0x0000 /* N & NO_INPUT/NO_OUPUT bits */
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#define QUP_ERROR_FLAGS_EN 0x030C
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#define QUP_ERR_MASK 0x3
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#define SPI_OUTPUT_FIFO_WORD_CNT 0x010C
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#define SPI_INPUT_FIFO_WORD_CNT 0x0214
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#define QUP_MX_WRITE_COUNT 0x0150
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#define QUP_MX_WRITE_CNT_CURRENT 0x0154
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#define QUP_CONFIG_SPI_MODE 0x0100
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#endif
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#define GSBI_CTRL_REG 0x0
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#define GSBI_SPI_CONFIG 0x30
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/* B-family only registers */
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#define QUP_HARDWARE_VER 0x0030
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#define QUP_HARDWARE_VER_2_1_1 0X20010001
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#define QUP_OPERATIONAL_MASK 0x0028
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#define QUP_OP_MASK_OUTPUT_SERVICE_FLAG 0x100
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#define QUP_OP_MASK_INPUT_SERVICE_FLAG 0x200
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#define QUP_ERROR_FLAGS 0x0308
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#define SPI_CONFIG QSD_REG(0x0000) QUP_REG(0x0300)
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#define SPI_IO_CONTROL QSD_REG(0x0004) QUP_REG(0x0304)
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#define SPI_IO_MODES QSD_REG(0x0008) QUP_REG(0x0008)
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#define SPI_SW_RESET QSD_REG(0x000C) QUP_REG(0x000C)
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#define SPI_TIME_OUT_CURRENT QSD_REG(0x0014) QUP_REG(0x0014)
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#define SPI_MX_OUTPUT_COUNT QSD_REG(0x0018) QUP_REG(0x0100)
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#define SPI_MX_OUTPUT_CNT_CURRENT QSD_REG(0x001C) QUP_REG(0x0104)
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#define SPI_MX_INPUT_COUNT QSD_REG(0x0020) QUP_REG(0x0200)
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#define SPI_MX_INPUT_CNT_CURRENT QSD_REG(0x0024) QUP_REG(0x0204)
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#define SPI_MX_READ_COUNT QSD_REG(0x0028) QUP_REG(0x0208)
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#define SPI_MX_READ_CNT_CURRENT QSD_REG(0x002C) QUP_REG(0x020C)
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#define SPI_OPERATIONAL QSD_REG(0x0030) QUP_REG(0x0018)
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#define SPI_ERROR_FLAGS QSD_REG(0x0034) QUP_REG(0x001C)
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#define SPI_ERROR_FLAGS_EN QSD_REG(0x0038) QUP_REG(0x0020)
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#define SPI_DEASSERT_WAIT QSD_REG(0x003C) QUP_REG(0x0310)
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#define SPI_OUTPUT_DEBUG QSD_REG(0x0040) QUP_REG(0x0108)
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#define SPI_INPUT_DEBUG QSD_REG(0x0044) QUP_REG(0x0210)
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#define SPI_TEST_CTRL QSD_REG(0x004C) QUP_REG(0x0024)
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#define SPI_OUTPUT_FIFO QSD_REG(0x0100) QUP_REG(0x0110)
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#define SPI_INPUT_FIFO QSD_REG(0x0200) QUP_REG(0x0218)
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#define SPI_STATE QSD_REG(SPI_OPERATIONAL) QUP_REG(0x0004)
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/* QUP_CONFIG fields */
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#define SPI_CFG_N 0x0000001F
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#define SPI_NO_INPUT 0x00000080
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#define SPI_NO_OUTPUT 0x00000040
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#define SPI_EN_EXT_OUT_FLAG 0x00010000
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/* SPI_CONFIG fields */
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#define SPI_CFG_LOOPBACK 0x00000100
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#define SPI_CFG_INPUT_FIRST 0x00000200
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#define SPI_CFG_HS_MODE 0x00000400
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/* SPI_IO_CONTROL fields */
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#define SPI_IO_C_FORCE_CS 0x00000800
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#define SPI_IO_C_CLK_IDLE_HIGH 0x00000400
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#define SPI_IO_C_MX_CS_MODE 0x00000100
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#define SPI_IO_C_CS_N_POLARITY 0x000000F0
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#define SPI_IO_C_CS_N_POLARITY_0 0x00000010
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#define SPI_IO_C_CS_SELECT 0x0000000C
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#define SPI_IO_C_TRISTATE_CS 0x00000002
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#define SPI_IO_C_NO_TRI_STATE 0x00000001
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/* SPI_IO_MODES fields */
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#define SPI_IO_M_OUTPUT_BIT_SHIFT_EN QSD_REG(0x00004000) QUP_REG(0x00010000)
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#define SPI_IO_M_PACK_EN QSD_REG(0x00002000) QUP_REG(0x00008000)
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#define SPI_IO_M_UNPACK_EN QSD_REG(0x00001000) QUP_REG(0x00004000)
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#define SPI_IO_M_INPUT_MODE QSD_REG(0x00000C00) QUP_REG(0x00003000)
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#define SPI_IO_M_OUTPUT_MODE QSD_REG(0x00000300) QUP_REG(0x00000C00)
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#define SPI_IO_M_INPUT_FIFO_SIZE QSD_REG(0x000000C0) QUP_REG(0x00000380)
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#define SPI_IO_M_INPUT_BLOCK_SIZE QSD_REG(0x00000030) QUP_REG(0x00000060)
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#define SPI_IO_M_OUTPUT_FIFO_SIZE QSD_REG(0x0000000C) QUP_REG(0x0000001C)
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#define SPI_IO_M_OUTPUT_BLOCK_SIZE QSD_REG(0x00000003) QUP_REG(0x00000003)
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#define INPUT_BLOCK_SZ_SHIFT QSD_REG(4) QUP_REG(5)
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#define INPUT_FIFO_SZ_SHIFT QSD_REG(6) QUP_REG(7)
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#define OUTPUT_BLOCK_SZ_SHIFT QSD_REG(0) QUP_REG(0)
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#define OUTPUT_FIFO_SZ_SHIFT QSD_REG(2) QUP_REG(2)
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#define OUTPUT_MODE_SHIFT QSD_REG(8) QUP_REG(10)
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#define INPUT_MODE_SHIFT QSD_REG(10) QUP_REG(12)
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/* SPI_OPERATIONAL fields */
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#define SPI_OP_MAX_INPUT_DONE_FLAG 0x00000800
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#define SPI_OP_MAX_OUTPUT_DONE_FLAG 0x00000400
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#define SPI_OP_INPUT_SERVICE_FLAG 0x00000200
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#define SPI_OP_OUTPUT_SERVICE_FLAG 0x00000100
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#define SPI_OP_INPUT_FIFO_FULL 0x00000080
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#define SPI_OP_OUTPUT_FIFO_FULL 0x00000040
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#define SPI_OP_IP_FIFO_NOT_EMPTY 0x00000020
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#define SPI_OP_OP_FIFO_NOT_EMPTY 0x00000010
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#define SPI_OP_STATE_VALID 0x00000004
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#define SPI_OP_STATE 0x00000003
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#define SPI_OP_STATE_CLEAR_BITS 0x2
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enum msm_spi_state {
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SPI_OP_STATE_RESET = 0x00000000,
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SPI_OP_STATE_RUN = 0x00000001,
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SPI_OP_STATE_PAUSE = 0x00000003,
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};
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/* SPI_ERROR_FLAGS fields */
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#define SPI_ERR_OUTPUT_OVER_RUN_ERR 0x00000020
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#define SPI_ERR_INPUT_UNDER_RUN_ERR 0x00000010
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#define SPI_ERR_OUTPUT_UNDER_RUN_ERR 0x00000008
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#define SPI_ERR_INPUT_OVER_RUN_ERR 0x00000004
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#define SPI_ERR_CLK_OVER_RUN_ERR 0x00000002
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#define SPI_ERR_CLK_UNDER_RUN_ERR 0x00000001
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/* We don't allow transactions larger than 4K-64 or 64K-64 due to
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mx_input/output_cnt register size */
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#define SPI_MAX_TRANSFERS QSD_REG(0xFC0) QUP_REG(0xFC0)
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#define SPI_MAX_LEN (SPI_MAX_TRANSFERS * dd->bytes_per_word)
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#define SPI_NUM_CHIPSELECTS 4
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#define SPI_SUPPORTED_MODES (SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_LOOP)
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/* high speed mode is when bus rate is greater then 26MHz */
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#define SPI_HS_MIN_RATE (26000000)
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#define SPI_DELAY_THRESHOLD 1
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/* Default timeout is 10 milliseconds */
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#define SPI_DEFAULT_TIMEOUT 10
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/* 250 microseconds */
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#define SPI_TRYLOCK_DELAY 250
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/* Data Mover burst size */
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#define DM_BURST_SIZE 16
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/* Data Mover commands should be aligned to 64 bit(8 bytes) */
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#define DM_BYTE_ALIGN 8
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enum msm_spi_qup_version {
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SPI_QUP_VERSION_NONE = 0x0,
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SPI_QUP_VERSION_BFAM = 0x2,
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};
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enum msm_spi_pipe_direction {
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SPI_BAM_CONSUMER_PIPE = 0x0,
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SPI_BAM_PRODUCER_PIPE = 0x1,
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};
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#define SPI_BAM_MAX_DESC_NUM 32
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#define SPI_MAX_TRFR_BTWN_RESETS ((64 * 1024) - 16) /* 64KB - 16byte */
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enum msm_spi_clk_path_vec_idx {
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MSM_SPI_CLK_PATH_SUSPEND_VEC = 0,
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MSM_SPI_CLK_PATH_RESUME_VEC = 1,
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};
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#define MSM_SPI_CLK_PATH_AVRG_BW(dd) (dd->pdata->max_clock_speed * 8)
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#define MSM_SPI_CLK_PATH_BRST_BW(dd) (dd->pdata->max_clock_speed * 8)
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static char const * const spi_rsrcs[] = {
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"spi_clk",
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"spi_miso",
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"spi_mosi"
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};
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static char const * const spi_cs_rsrcs[] = {
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"spi_cs",
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"spi_cs1",
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"spi_cs2",
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"spi_cs3",
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};
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enum msm_spi_mode {
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SPI_FIFO_MODE = 0x0, /* 00 */
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SPI_BLOCK_MODE = 0x1, /* 01 */
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SPI_DMOV_MODE = 0x2, /* 10 */
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SPI_BAM_MODE = 0x3, /* 11 */
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SPI_MODE_NONE = 0xFF, /* invalid value */
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};
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/* Structure for SPI CS GPIOs */
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struct spi_cs_gpio {
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int gpio_num;
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bool valid;
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};
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/* Structures for Data Mover */
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struct spi_dmov_cmd {
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dmov_box box; /* data aligned to max(dm_burst_size, block_size)
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(<= fifo_size) */
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dmov_s single_pad; /* data unaligned to max(dm_burst_size, block_size)
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padded to fit */
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dma_addr_t cmd_ptr;
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};
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static struct pm_qos_request qos_req_list;
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#ifdef CONFIG_DEBUG_FS
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/* Used to create debugfs entries */
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static const struct {
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const char *name;
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mode_t mode;
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int offset;
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} debugfs_spi_regs[] = {
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{"config", S_IRUGO | S_IWUSR, SPI_CONFIG},
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{"io_control", S_IRUGO | S_IWUSR, SPI_IO_CONTROL},
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{"io_modes", S_IRUGO | S_IWUSR, SPI_IO_MODES},
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{"sw_reset", S_IWUSR, SPI_SW_RESET},
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{"time_out_current", S_IRUGO, SPI_TIME_OUT_CURRENT},
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{"mx_output_count", S_IRUGO | S_IWUSR, SPI_MX_OUTPUT_COUNT},
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{"mx_output_cnt_current", S_IRUGO, SPI_MX_OUTPUT_CNT_CURRENT},
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{"mx_input_count", S_IRUGO | S_IWUSR, SPI_MX_INPUT_COUNT},
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{"mx_input_cnt_current", S_IRUGO, SPI_MX_INPUT_CNT_CURRENT},
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{"mx_read_count", S_IRUGO | S_IWUSR, SPI_MX_READ_COUNT},
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{"mx_read_cnt_current", S_IRUGO, SPI_MX_READ_CNT_CURRENT},
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{"operational", S_IRUGO | S_IWUSR, SPI_OPERATIONAL},
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{"error_flags", S_IRUGO | S_IWUSR, SPI_ERROR_FLAGS},
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{"error_flags_en", S_IRUGO | S_IWUSR, SPI_ERROR_FLAGS_EN},
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{"deassert_wait", S_IRUGO | S_IWUSR, SPI_DEASSERT_WAIT},
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{"output_debug", S_IRUGO, SPI_OUTPUT_DEBUG},
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{"input_debug", S_IRUGO, SPI_INPUT_DEBUG},
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{"test_ctrl", S_IRUGO | S_IWUSR, SPI_TEST_CTRL},
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{"output_fifo", S_IWUSR, SPI_OUTPUT_FIFO},
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{"input_fifo" , S_IRUSR, SPI_INPUT_FIFO},
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{"spi_state", S_IRUGO | S_IWUSR, SPI_STATE},
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#if defined(CONFIG_SPI_QSD) || defined(CONFIG_SPI_QSD_MODULE)
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{"fifo_word_cnt", S_IRUGO, SPI_FIFO_WORD_CNT},
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#else
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{"qup_config", S_IRUGO | S_IWUSR, QUP_CONFIG},
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{"qup_error_flags", S_IRUGO | S_IWUSR, QUP_ERROR_FLAGS},
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{"qup_error_flags_en", S_IRUGO | S_IWUSR, QUP_ERROR_FLAGS_EN},
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{"mx_write_cnt", S_IRUGO | S_IWUSR, QUP_MX_WRITE_COUNT},
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{"mx_write_cnt_current", S_IRUGO, QUP_MX_WRITE_CNT_CURRENT},
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{"output_fifo_word_cnt", S_IRUGO, SPI_OUTPUT_FIFO_WORD_CNT},
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{"input_fifo_word_cnt", S_IRUGO, SPI_INPUT_FIFO_WORD_CNT},
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#endif
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};
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#endif
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/**
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* qup_i2c_clk_path_vote: data to use bus scaling driver for clock path vote
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*
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* @client_hdl when zero, client is not registered with the bus scaling driver,
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* and bus scaling functionality should not be used. When non zero, it
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* is a bus scaling client id and may be used to vote for clock path.
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* @reg_err when true, registration error was detected and an error message was
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* logged. i2c will attempt to re-register but will log error only once.
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* once registration succeed, the flag is set to false.
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*/
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struct qup_i2c_clk_path_vote {
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u32 client_hdl;
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struct msm_bus_scale_pdata *pdata;
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bool reg_err;
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};
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struct msm_spi_bam_pipe {
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struct sps_pipe *handle;
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struct sps_connect config;
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bool teardown_required;
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};
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struct msm_spi_bam {
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void __iomem *base;
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u32 phys_addr;
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u32 handle;
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u32 irq;
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struct msm_spi_bam_pipe prod;
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struct msm_spi_bam_pipe cons;
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bool deregister_required;
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};
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struct msm_spi {
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u8 *read_buf;
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const u8 *write_buf;
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void __iomem *base;
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struct device *dev;
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spinlock_t queue_lock;
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struct mutex core_lock;
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struct list_head queue;
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struct workqueue_struct *workqueue;
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struct work_struct work_data;
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struct spi_message *cur_msg;
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struct spi_transfer *cur_transfer;
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struct completion transfer_complete;
|
||
|
|
struct clk *clk; /* core clock */
|
||
|
|
struct clk *pclk; /* interface clock */
|
||
|
|
struct qup_i2c_clk_path_vote clk_path_vote;
|
||
|
|
unsigned long mem_phys_addr;
|
||
|
|
size_t mem_size;
|
||
|
|
int input_fifo_size;
|
||
|
|
int output_fifo_size;
|
||
|
|
u32 rx_bytes_remaining;
|
||
|
|
u32 tx_bytes_remaining;
|
||
|
|
u32 clock_speed;
|
||
|
|
int irq_in;
|
||
|
|
int read_xfr_cnt;
|
||
|
|
int write_xfr_cnt;
|
||
|
|
int write_len;
|
||
|
|
int read_len;
|
||
|
|
#if defined(CONFIG_SPI_QSD) || defined(CONFIG_SPI_QSD_MODULE)
|
||
|
|
int irq_out;
|
||
|
|
int irq_err;
|
||
|
|
#endif
|
||
|
|
int bytes_per_word;
|
||
|
|
bool suspended;
|
||
|
|
bool transfer_pending;
|
||
|
|
wait_queue_head_t continue_suspend;
|
||
|
|
/* DMA data */
|
||
|
|
enum msm_spi_mode mode;
|
||
|
|
bool use_dma;
|
||
|
|
int tx_dma_chan;
|
||
|
|
int tx_dma_crci;
|
||
|
|
int rx_dma_chan;
|
||
|
|
int rx_dma_crci;
|
||
|
|
int (*dma_init) (struct msm_spi *dd);
|
||
|
|
void (*dma_teardown) (struct msm_spi *dd);
|
||
|
|
struct msm_spi_bam bam;
|
||
|
|
/* Data Mover Commands */
|
||
|
|
struct spi_dmov_cmd *tx_dmov_cmd;
|
||
|
|
struct spi_dmov_cmd *rx_dmov_cmd;
|
||
|
|
/* Physical address of the tx dmov box command */
|
||
|
|
dma_addr_t tx_dmov_cmd_dma;
|
||
|
|
dma_addr_t rx_dmov_cmd_dma;
|
||
|
|
struct msm_dmov_cmd tx_hdr;
|
||
|
|
struct msm_dmov_cmd rx_hdr;
|
||
|
|
int input_block_size;
|
||
|
|
int output_block_size;
|
||
|
|
int input_burst_size;
|
||
|
|
int output_burst_size;
|
||
|
|
atomic_t rx_irq_called;
|
||
|
|
atomic_t tx_irq_called;
|
||
|
|
/* Used to pad messages unaligned to block size */
|
||
|
|
u8 *tx_padding;
|
||
|
|
dma_addr_t tx_padding_dma;
|
||
|
|
u8 *rx_padding;
|
||
|
|
dma_addr_t rx_padding_dma;
|
||
|
|
u32 tx_unaligned_len;
|
||
|
|
u32 rx_unaligned_len;
|
||
|
|
/* DMA statistics */
|
||
|
|
int stat_dmov_tx_err;
|
||
|
|
int stat_dmov_rx_err;
|
||
|
|
int stat_rx;
|
||
|
|
int stat_dmov_rx;
|
||
|
|
int stat_tx;
|
||
|
|
int stat_dmov_tx;
|
||
|
|
#ifdef CONFIG_DEBUG_FS
|
||
|
|
struct dentry *dent_spi;
|
||
|
|
struct dentry *debugfs_spi_regs[ARRAY_SIZE(debugfs_spi_regs)];
|
||
|
|
#endif
|
||
|
|
struct msm_spi_platform_data *pdata; /* Platform data */
|
||
|
|
/* Remote Spinlock Data */
|
||
|
|
bool use_rlock;
|
||
|
|
remote_mutex_t r_lock;
|
||
|
|
uint32_t pm_lat;
|
||
|
|
/* When set indicates multiple transfers in a single message */
|
||
|
|
bool multi_xfr;
|
||
|
|
bool done;
|
||
|
|
u32 cur_msg_len;
|
||
|
|
/* Used in FIFO mode to keep track of the transfer being processed */
|
||
|
|
struct spi_transfer *cur_tx_transfer;
|
||
|
|
struct spi_transfer *cur_rx_transfer;
|
||
|
|
/* Temporary buffer used for WR-WR or WR-RD transfers */
|
||
|
|
u8 *temp_buf;
|
||
|
|
/* GPIO pin numbers for SPI clk, miso and mosi */
|
||
|
|
int spi_gpios[ARRAY_SIZE(spi_rsrcs)];
|
||
|
|
/* SPI CS GPIOs for each slave */
|
||
|
|
struct spi_cs_gpio cs_gpios[ARRAY_SIZE(spi_cs_rsrcs)];
|
||
|
|
enum msm_spi_qup_version qup_ver;
|
||
|
|
int max_trfr_len;
|
||
|
|
};
|
||
|
|
|
||
|
|
/* Forward declaration */
|
||
|
|
static irqreturn_t msm_spi_input_irq(int irq, void *dev_id);
|
||
|
|
static irqreturn_t msm_spi_output_irq(int irq, void *dev_id);
|
||
|
|
static irqreturn_t msm_spi_error_irq(int irq, void *dev_id);
|
||
|
|
static inline int msm_spi_set_state(struct msm_spi *dd,
|
||
|
|
enum msm_spi_state state);
|
||
|
|
static void msm_spi_write_word_to_fifo(struct msm_spi *dd);
|
||
|
|
static inline void msm_spi_write_rmn_to_fifo(struct msm_spi *dd);
|
||
|
|
static irqreturn_t msm_spi_qup_irq(int irq, void *dev_id);
|
||
|
|
|
||
|
|
#if defined(CONFIG_SPI_QSD) || defined(CONFIG_SPI_QSD_MODULE)
|
||
|
|
static inline void msm_spi_disable_irqs(struct msm_spi *dd)
|
||
|
|
{
|
||
|
|
disable_irq(dd->irq_in);
|
||
|
|
disable_irq(dd->irq_out);
|
||
|
|
disable_irq(dd->irq_err);
|
||
|
|
}
|
||
|
|
|
||
|
|
static inline void msm_spi_enable_irqs(struct msm_spi *dd)
|
||
|
|
{
|
||
|
|
enable_irq(dd->irq_in);
|
||
|
|
enable_irq(dd->irq_out);
|
||
|
|
enable_irq(dd->irq_err);
|
||
|
|
}
|
||
|
|
|
||
|
|
static inline int msm_spi_request_irq(struct msm_spi *dd,
|
||
|
|
struct platform_device *pdev,
|
||
|
|
struct spi_master *master)
|
||
|
|
{
|
||
|
|
int rc;
|
||
|
|
|
||
|
|
dd->irq_in = platform_get_irq(pdev, 0);
|
||
|
|
dd->irq_out = platform_get_irq(pdev, 1);
|
||
|
|
dd->irq_err = platform_get_irq(pdev, 2);
|
||
|
|
if ((dd->irq_in < 0) || (dd->irq_out < 0) || (dd->irq_err < 0))
|
||
|
|
return -EINVAL;
|
||
|
|
|
||
|
|
rc = devm_request_irq(dd->dev, dd->irq_in, msm_spi_input_irq,
|
||
|
|
IRQF_TRIGGER_RISING, pdev->name, dd);
|
||
|
|
if (rc)
|
||
|
|
goto error_irq;
|
||
|
|
|
||
|
|
rc = devm_request_irq(dd->dev, dd->irq_out, msm_spi_output_irq,
|
||
|
|
IRQF_TRIGGER_RISING, pdev->name, dd);
|
||
|
|
if (rc)
|
||
|
|
goto error_irq;
|
||
|
|
|
||
|
|
rc = devm_request_irq(dd->dev, dd->irq_err, msm_spi_error_irq,
|
||
|
|
IRQF_TRIGGER_RISING, pdev->name, master);
|
||
|
|
if (rc)
|
||
|
|
goto error_irq;
|
||
|
|
|
||
|
|
error_irq:
|
||
|
|
return rc;
|
||
|
|
}
|
||
|
|
|
||
|
|
static inline void msm_spi_get_clk_err(struct msm_spi *dd, u32 *spi_err) {}
|
||
|
|
static inline void msm_spi_ack_clk_err(struct msm_spi *dd) {}
|
||
|
|
static inline void msm_spi_set_qup_config(struct msm_spi *dd, int bpw) {}
|
||
|
|
|
||
|
|
static inline int msm_spi_prepare_for_write(struct msm_spi *dd) { return 0; }
|
||
|
|
static inline void msm_spi_start_write(struct msm_spi *dd, u32 read_count)
|
||
|
|
{
|
||
|
|
msm_spi_write_word_to_fifo(dd);
|
||
|
|
}
|
||
|
|
static inline void msm_spi_set_write_count(struct msm_spi *dd, int val) {}
|
||
|
|
|
||
|
|
static inline void msm_spi_complete(struct msm_spi *dd)
|
||
|
|
{
|
||
|
|
complete(&dd->transfer_complete);
|
||
|
|
}
|
||
|
|
|
||
|
|
static inline void msm_spi_enable_error_flags(struct msm_spi *dd)
|
||
|
|
{
|
||
|
|
writel_relaxed(0x0000007B, dd->base + SPI_ERROR_FLAGS_EN);
|
||
|
|
}
|
||
|
|
|
||
|
|
static inline void msm_spi_clear_error_flags(struct msm_spi *dd)
|
||
|
|
{
|
||
|
|
writel_relaxed(0x0000007F, dd->base + SPI_ERROR_FLAGS);
|
||
|
|
}
|
||
|
|
|
||
|
|
#else
|
||
|
|
/* In QUP the same interrupt line is used for input, output and error*/
|
||
|
|
static inline int msm_spi_request_irq(struct msm_spi *dd,
|
||
|
|
struct platform_device *pdev,
|
||
|
|
struct spi_master *master)
|
||
|
|
{
|
||
|
|
dd->irq_in = platform_get_irq(pdev, 0);
|
||
|
|
if (dd->irq_in < 0)
|
||
|
|
return -EINVAL;
|
||
|
|
|
||
|
|
return devm_request_irq(dd->dev, dd->irq_in, msm_spi_qup_irq,
|
||
|
|
IRQF_TRIGGER_HIGH, pdev->name, dd);
|
||
|
|
}
|
||
|
|
|
||
|
|
static inline void msm_spi_disable_irqs(struct msm_spi *dd)
|
||
|
|
{
|
||
|
|
disable_irq(dd->irq_in);
|
||
|
|
}
|
||
|
|
|
||
|
|
static inline void msm_spi_enable_irqs(struct msm_spi *dd)
|
||
|
|
{
|
||
|
|
enable_irq(dd->irq_in);
|
||
|
|
}
|
||
|
|
|
||
|
|
static inline void msm_spi_get_clk_err(struct msm_spi *dd, u32 *spi_err)
|
||
|
|
{
|
||
|
|
*spi_err = readl_relaxed(dd->base + QUP_ERROR_FLAGS);
|
||
|
|
}
|
||
|
|
|
||
|
|
static inline void msm_spi_ack_clk_err(struct msm_spi *dd)
|
||
|
|
{
|
||
|
|
writel_relaxed(QUP_ERR_MASK, dd->base + QUP_ERROR_FLAGS);
|
||
|
|
}
|
||
|
|
|
||
|
|
static inline void
|
||
|
|
msm_spi_set_bpw_and_no_io_flags(struct msm_spi *dd, u32 *config, int n);
|
||
|
|
|
||
|
|
/**
|
||
|
|
* msm_spi_set_qup_config: set QUP_CONFIG to no_input, no_output, and N bits
|
||
|
|
*/
|
||
|
|
static inline void msm_spi_set_qup_config(struct msm_spi *dd, int bpw)
|
||
|
|
{
|
||
|
|
u32 qup_config = readl_relaxed(dd->base + QUP_CONFIG);
|
||
|
|
|
||
|
|
msm_spi_set_bpw_and_no_io_flags(dd, &qup_config, bpw-1);
|
||
|
|
writel_relaxed(qup_config | QUP_CONFIG_SPI_MODE, dd->base + QUP_CONFIG);
|
||
|
|
}
|
||
|
|
|
||
|
|
static inline int msm_spi_prepare_for_write(struct msm_spi *dd)
|
||
|
|
{
|
||
|
|
if (msm_spi_set_state(dd, SPI_OP_STATE_RUN))
|
||
|
|
return -EINVAL;
|
||
|
|
if (msm_spi_set_state(dd, SPI_OP_STATE_PAUSE))
|
||
|
|
return -EINVAL;
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
|
||
|
|
static inline void msm_spi_start_write(struct msm_spi *dd, u32 read_count)
|
||
|
|
{
|
||
|
|
if (read_count <= dd->input_fifo_size)
|
||
|
|
msm_spi_write_rmn_to_fifo(dd);
|
||
|
|
else
|
||
|
|
msm_spi_write_word_to_fifo(dd);
|
||
|
|
}
|
||
|
|
|
||
|
|
static inline void msm_spi_set_write_count(struct msm_spi *dd, int val)
|
||
|
|
{
|
||
|
|
writel_relaxed(val, dd->base + QUP_MX_WRITE_COUNT);
|
||
|
|
}
|
||
|
|
|
||
|
|
static inline void msm_spi_complete(struct msm_spi *dd)
|
||
|
|
{
|
||
|
|
dd->done = 1;
|
||
|
|
}
|
||
|
|
|
||
|
|
static inline void msm_spi_enable_error_flags(struct msm_spi *dd)
|
||
|
|
{
|
||
|
|
if (dd->qup_ver == SPI_QUP_VERSION_BFAM)
|
||
|
|
writel_relaxed(
|
||
|
|
SPI_ERR_CLK_UNDER_RUN_ERR | SPI_ERR_CLK_OVER_RUN_ERR,
|
||
|
|
dd->base + SPI_ERROR_FLAGS_EN);
|
||
|
|
else
|
||
|
|
writel_relaxed(0x00000078, dd->base + SPI_ERROR_FLAGS_EN);
|
||
|
|
}
|
||
|
|
|
||
|
|
static inline void msm_spi_clear_error_flags(struct msm_spi *dd)
|
||
|
|
{
|
||
|
|
if (dd->qup_ver == SPI_QUP_VERSION_BFAM)
|
||
|
|
writel_relaxed(
|
||
|
|
SPI_ERR_CLK_UNDER_RUN_ERR | SPI_ERR_CLK_OVER_RUN_ERR,
|
||
|
|
dd->base + SPI_ERROR_FLAGS);
|
||
|
|
else
|
||
|
|
writel_relaxed(0x0000007C, dd->base + SPI_ERROR_FLAGS);
|
||
|
|
}
|
||
|
|
|
||
|
|
#endif
|
||
|
|
#endif
|