439 lines
18 KiB
C
439 lines
18 KiB
C
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/* Copyright (c) 2002,2007-2012, The Linux Foundation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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* only version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*/
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#ifndef __A200_REG_H
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#define __A200_REG_H
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enum VGT_EVENT_TYPE {
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VS_DEALLOC = 0,
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PS_DEALLOC = 1,
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VS_DONE_TS = 2,
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PS_DONE_TS = 3,
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CACHE_FLUSH_TS = 4,
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CONTEXT_DONE = 5,
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CACHE_FLUSH = 6,
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VIZQUERY_START = 7,
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VIZQUERY_END = 8,
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SC_WAIT_WC = 9,
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RST_PIX_CNT = 13,
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RST_VTX_CNT = 14,
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TILE_FLUSH = 15,
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CACHE_FLUSH_AND_INV_TS_EVENT = 20,
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ZPASS_DONE = 21,
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CACHE_FLUSH_AND_INV_EVENT = 22,
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PERFCOUNTER_START = 23,
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PERFCOUNTER_STOP = 24,
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VS_FETCH_DONE = 27,
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FACENESS_FLUSH = 28,
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};
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enum COLORFORMATX {
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COLORX_4_4_4_4 = 0,
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COLORX_1_5_5_5 = 1,
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COLORX_5_6_5 = 2,
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COLORX_8 = 3,
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COLORX_8_8 = 4,
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COLORX_8_8_8_8 = 5,
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COLORX_S8_8_8_8 = 6,
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COLORX_16_FLOAT = 7,
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COLORX_16_16_FLOAT = 8,
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COLORX_16_16_16_16_FLOAT = 9,
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COLORX_32_FLOAT = 10,
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COLORX_32_32_FLOAT = 11,
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COLORX_32_32_32_32_FLOAT = 12,
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COLORX_2_3_3 = 13,
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COLORX_8_8_8 = 14,
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};
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enum SURFACEFORMAT {
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FMT_1_REVERSE = 0,
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FMT_1 = 1,
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FMT_8 = 2,
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FMT_1_5_5_5 = 3,
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FMT_5_6_5 = 4,
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FMT_6_5_5 = 5,
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FMT_8_8_8_8 = 6,
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FMT_2_10_10_10 = 7,
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FMT_8_A = 8,
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FMT_8_B = 9,
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FMT_8_8 = 10,
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FMT_Cr_Y1_Cb_Y0 = 11,
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FMT_Y1_Cr_Y0_Cb = 12,
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FMT_5_5_5_1 = 13,
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FMT_8_8_8_8_A = 14,
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FMT_4_4_4_4 = 15,
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FMT_10_11_11 = 16,
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FMT_11_11_10 = 17,
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FMT_DXT1 = 18,
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FMT_DXT2_3 = 19,
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FMT_DXT4_5 = 20,
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FMT_24_8 = 22,
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FMT_24_8_FLOAT = 23,
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FMT_16 = 24,
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FMT_16_16 = 25,
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FMT_16_16_16_16 = 26,
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FMT_16_EXPAND = 27,
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FMT_16_16_EXPAND = 28,
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FMT_16_16_16_16_EXPAND = 29,
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FMT_16_FLOAT = 30,
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FMT_16_16_FLOAT = 31,
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FMT_16_16_16_16_FLOAT = 32,
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FMT_32 = 33,
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FMT_32_32 = 34,
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FMT_32_32_32_32 = 35,
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FMT_32_FLOAT = 36,
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FMT_32_32_FLOAT = 37,
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FMT_32_32_32_32_FLOAT = 38,
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FMT_32_AS_8 = 39,
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FMT_32_AS_8_8 = 40,
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FMT_16_MPEG = 41,
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FMT_16_16_MPEG = 42,
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FMT_8_INTERLACED = 43,
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FMT_32_AS_8_INTERLACED = 44,
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FMT_32_AS_8_8_INTERLACED = 45,
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FMT_16_INTERLACED = 46,
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FMT_16_MPEG_INTERLACED = 47,
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FMT_16_16_MPEG_INTERLACED = 48,
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FMT_DXN = 49,
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FMT_8_8_8_8_AS_16_16_16_16 = 50,
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FMT_DXT1_AS_16_16_16_16 = 51,
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FMT_DXT2_3_AS_16_16_16_16 = 52,
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FMT_DXT4_5_AS_16_16_16_16 = 53,
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FMT_2_10_10_10_AS_16_16_16_16 = 54,
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FMT_10_11_11_AS_16_16_16_16 = 55,
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FMT_11_11_10_AS_16_16_16_16 = 56,
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FMT_32_32_32_FLOAT = 57,
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FMT_DXT3A = 58,
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FMT_DXT5A = 59,
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FMT_CTX1 = 60,
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FMT_DXT3A_AS_1_1_1_1 = 61
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};
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#define REG_PERF_MODE_CNT 0x0
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#define REG_PERF_STATE_RESET 0x0
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#define REG_PERF_STATE_ENABLE 0x1
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#define REG_PERF_STATE_FREEZE 0x2
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#define RB_EDRAM_INFO_EDRAM_SIZE_SIZE 4
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#define RB_EDRAM_INFO_EDRAM_MAPPING_MODE_SIZE 2
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#define RB_EDRAM_INFO_UNUSED0_SIZE 8
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#define RB_EDRAM_INFO_EDRAM_RANGE_SIZE 18
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struct rb_edram_info_t {
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unsigned int edram_size:RB_EDRAM_INFO_EDRAM_SIZE_SIZE;
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unsigned int edram_mapping_mode:RB_EDRAM_INFO_EDRAM_MAPPING_MODE_SIZE;
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unsigned int unused0:RB_EDRAM_INFO_UNUSED0_SIZE;
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unsigned int edram_range:RB_EDRAM_INFO_EDRAM_RANGE_SIZE;
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};
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union reg_rb_edram_info {
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unsigned int val;
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struct rb_edram_info_t f;
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};
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#define RBBM_READ_ERROR_ADDRESS_MASK 0x0001fffc
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#define RBBM_READ_ERROR_REQUESTER (1<<30)
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#define RBBM_READ_ERROR_ERROR (1<<31)
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#define CP_RB_CNTL_RB_BUFSZ_SIZE 6
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#define CP_RB_CNTL_UNUSED0_SIZE 2
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#define CP_RB_CNTL_RB_BLKSZ_SIZE 6
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#define CP_RB_CNTL_UNUSED1_SIZE 2
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#define CP_RB_CNTL_BUF_SWAP_SIZE 2
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#define CP_RB_CNTL_UNUSED2_SIZE 2
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#define CP_RB_CNTL_RB_POLL_EN_SIZE 1
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#define CP_RB_CNTL_UNUSED3_SIZE 6
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#define CP_RB_CNTL_RB_NO_UPDATE_SIZE 1
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#define CP_RB_CNTL_UNUSED4_SIZE 3
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#define CP_RB_CNTL_RB_RPTR_WR_ENA_SIZE 1
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struct cp_rb_cntl_t {
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unsigned int rb_bufsz:CP_RB_CNTL_RB_BUFSZ_SIZE;
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unsigned int unused0:CP_RB_CNTL_UNUSED0_SIZE;
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unsigned int rb_blksz:CP_RB_CNTL_RB_BLKSZ_SIZE;
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unsigned int unused1:CP_RB_CNTL_UNUSED1_SIZE;
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unsigned int buf_swap:CP_RB_CNTL_BUF_SWAP_SIZE;
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unsigned int unused2:CP_RB_CNTL_UNUSED2_SIZE;
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unsigned int rb_poll_en:CP_RB_CNTL_RB_POLL_EN_SIZE;
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unsigned int unused3:CP_RB_CNTL_UNUSED3_SIZE;
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unsigned int rb_no_update:CP_RB_CNTL_RB_NO_UPDATE_SIZE;
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unsigned int unused4:CP_RB_CNTL_UNUSED4_SIZE;
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unsigned int rb_rptr_wr_ena:CP_RB_CNTL_RB_RPTR_WR_ENA_SIZE;
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};
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union reg_cp_rb_cntl {
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unsigned int val:32;
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struct cp_rb_cntl_t f;
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};
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#define RB_COLOR_INFO__COLOR_FORMAT_MASK 0x0000000fL
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#define RB_COPY_DEST_INFO__COPY_DEST_FORMAT__SHIFT 0x00000004
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#define SQ_INT_CNTL__PS_WATCHDOG_MASK 0x00000001L
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#define SQ_INT_CNTL__VS_WATCHDOG_MASK 0x00000002L
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#define RBBM_INT_CNTL__RDERR_INT_MASK 0x00000001L
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#define RBBM_INT_CNTL__DISPLAY_UPDATE_INT_MASK 0x00000002L
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#define RBBM_INT_CNTL__GUI_IDLE_INT_MASK 0x00080000L
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#define RBBM_STATUS__CMDFIFO_AVAIL_MASK 0x0000001fL
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#define RBBM_STATUS__TC_BUSY_MASK 0x00000020L
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#define RBBM_STATUS__HIRQ_PENDING_MASK 0x00000100L
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#define RBBM_STATUS__CPRQ_PENDING_MASK 0x00000200L
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#define RBBM_STATUS__CFRQ_PENDING_MASK 0x00000400L
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#define RBBM_STATUS__PFRQ_PENDING_MASK 0x00000800L
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#define RBBM_STATUS__VGT_BUSY_NO_DMA_MASK 0x00001000L
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#define RBBM_STATUS__RBBM_WU_BUSY_MASK 0x00004000L
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#define RBBM_STATUS__CP_NRT_BUSY_MASK 0x00010000L
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#define RBBM_STATUS__MH_BUSY_MASK 0x00040000L
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#define RBBM_STATUS__MH_COHERENCY_BUSY_MASK 0x00080000L
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#define RBBM_STATUS__SX_BUSY_MASK 0x00200000L
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#define RBBM_STATUS__TPC_BUSY_MASK 0x00400000L
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#define RBBM_STATUS__SC_CNTX_BUSY_MASK 0x01000000L
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#define RBBM_STATUS__PA_BUSY_MASK 0x02000000L
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#define RBBM_STATUS__VGT_BUSY_MASK 0x04000000L
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#define RBBM_STATUS__SQ_CNTX17_BUSY_MASK 0x08000000L
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#define RBBM_STATUS__SQ_CNTX0_BUSY_MASK 0x10000000L
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#define RBBM_STATUS__RB_CNTX_BUSY_MASK 0x40000000L
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#define RBBM_STATUS__GUI_ACTIVE_MASK 0x80000000L
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#define CP_INT_CNTL__SW_INT_MASK 0x00080000L
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#define CP_INT_CNTL__T0_PACKET_IN_IB_MASK 0x00800000L
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#define CP_INT_CNTL__OPCODE_ERROR_MASK 0x01000000L
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#define CP_INT_CNTL__PROTECTED_MODE_ERROR_MASK 0x02000000L
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#define CP_INT_CNTL__RESERVED_BIT_ERROR_MASK 0x04000000L
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#define CP_INT_CNTL__IB_ERROR_MASK 0x08000000L
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#define CP_INT_CNTL__IB2_INT_MASK 0x20000000L
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#define CP_INT_CNTL__IB1_INT_MASK 0x40000000L
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#define CP_INT_CNTL__RB_INT_MASK 0x80000000L
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#define MASTER_INT_SIGNAL__MH_INT_STAT 0x00000020L
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#define MASTER_INT_SIGNAL__SQ_INT_STAT 0x04000000L
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#define MASTER_INT_SIGNAL__CP_INT_STAT 0x40000000L
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#define MASTER_INT_SIGNAL__RBBM_INT_STAT 0x80000000L
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#define RB_EDRAM_INFO__EDRAM_SIZE_MASK 0x0000000fL
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#define RB_EDRAM_INFO__EDRAM_RANGE_MASK 0xffffc000L
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#define MH_ARBITER_CONFIG__SAME_PAGE_GRANULARITY__SHIFT 0x00000006
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#define MH_ARBITER_CONFIG__L1_ARB_ENABLE__SHIFT 0x00000007
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#define MH_ARBITER_CONFIG__L1_ARB_HOLD_ENABLE__SHIFT 0x00000008
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#define MH_ARBITER_CONFIG__L2_ARB_CONTROL__SHIFT 0x00000009
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#define MH_ARBITER_CONFIG__PAGE_SIZE__SHIFT 0x0000000a
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#define MH_ARBITER_CONFIG__TC_REORDER_ENABLE__SHIFT 0x0000000d
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#define MH_ARBITER_CONFIG__TC_ARB_HOLD_ENABLE__SHIFT 0x0000000e
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#define MH_ARBITER_CONFIG__IN_FLIGHT_LIMIT_ENABLE__SHIFT 0x0000000f
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#define MH_ARBITER_CONFIG__IN_FLIGHT_LIMIT__SHIFT 0x00000010
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#define MH_ARBITER_CONFIG__CP_CLNT_ENABLE__SHIFT 0x00000016
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#define MH_ARBITER_CONFIG__VGT_CLNT_ENABLE__SHIFT 0x00000017
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#define MH_ARBITER_CONFIG__TC_CLNT_ENABLE__SHIFT 0x00000018
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#define MH_ARBITER_CONFIG__RB_CLNT_ENABLE__SHIFT 0x00000019
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#define MH_ARBITER_CONFIG__PA_CLNT_ENABLE__SHIFT 0x0000001a
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#define CP_RB_CNTL__RB_BUFSZ__SHIFT 0x00000000
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#define CP_RB_CNTL__RB_BLKSZ__SHIFT 0x00000008
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#define CP_RB_CNTL__RB_POLL_EN__SHIFT 0x00000014
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#define CP_RB_CNTL__RB_NO_UPDATE__SHIFT 0x0000001b
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#define RB_COLOR_INFO__COLOR_FORMAT__SHIFT 0x00000000
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#define RB_EDRAM_INFO__EDRAM_MAPPING_MODE__SHIFT 0x00000004
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#define RB_EDRAM_INFO__EDRAM_RANGE__SHIFT 0x0000000e
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#define REG_CP_CSQ_IB1_STAT 0x01FE
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#define REG_CP_CSQ_IB2_STAT 0x01FF
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#define REG_CP_CSQ_RB_STAT 0x01FD
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#define REG_CP_DEBUG 0x01FC
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#define REG_CP_IB1_BASE 0x0458
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#define REG_CP_IB1_BUFSZ 0x0459
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#define REG_CP_IB2_BASE 0x045A
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#define REG_CP_IB2_BUFSZ 0x045B
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#define REG_CP_INT_ACK 0x01F4
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#define REG_CP_INT_CNTL 0x01F2
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#define REG_CP_INT_STATUS 0x01F3
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#define REG_CP_ME_CNTL 0x01F6
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#define REG_CP_ME_RAM_DATA 0x01FA
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#define REG_CP_ME_RAM_WADDR 0x01F8
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#define REG_CP_ME_RAM_RADDR 0x01F9
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#define REG_CP_ME_STATUS 0x01F7
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#define REG_CP_PFP_UCODE_ADDR 0x00C0
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#define REG_CP_PFP_UCODE_DATA 0x00C1
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#define REG_CP_QUEUE_THRESHOLDS 0x01D5
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#define REG_CP_RB_BASE 0x01C0
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#define REG_CP_RB_CNTL 0x01C1
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#define REG_CP_RB_RPTR 0x01C4
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#define REG_CP_RB_RPTR_ADDR 0x01C3
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#define REG_CP_RB_RPTR_WR 0x01C7
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#define REG_CP_RB_WPTR 0x01C5
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#define REG_CP_RB_WPTR_BASE 0x01C8
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#define REG_CP_RB_WPTR_DELAY 0x01C6
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#define REG_CP_STAT 0x047F
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#define REG_CP_STATE_DEBUG_DATA 0x01ED
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#define REG_CP_STATE_DEBUG_INDEX 0x01EC
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#define REG_CP_ST_BASE 0x044D
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#define REG_CP_ST_BUFSZ 0x044E
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#define REG_CP_PERFMON_CNTL 0x0444
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#define REG_CP_PERFCOUNTER_SELECT 0x0445
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#define REG_CP_PERFCOUNTER_LO 0x0446
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#define REG_CP_PERFCOUNTER_HI 0x0447
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#define REG_RBBM_PERFCOUNTER1_SELECT 0x0395
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#define REG_RBBM_PERFCOUNTER1_HI 0x0398
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#define REG_RBBM_PERFCOUNTER1_LO 0x0397
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#define REG_MASTER_INT_SIGNAL 0x03B7
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#define REG_PA_CL_VPORT_XSCALE 0x210F
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#define REG_PA_CL_VPORT_ZOFFSET 0x2114
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#define REG_PA_CL_VPORT_ZSCALE 0x2113
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#define REG_PA_CL_CLIP_CNTL 0x2204
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#define REG_PA_CL_VTE_CNTL 0x2206
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#define REG_PA_SC_AA_MASK 0x2312
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#define REG_PA_SC_LINE_CNTL 0x2300
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||
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#define REG_PA_SC_SCREEN_SCISSOR_BR 0x200F
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#define REG_PA_SC_SCREEN_SCISSOR_TL 0x200E
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#define REG_PA_SC_VIZ_QUERY 0x2293
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#define REG_PA_SC_VIZ_QUERY_STATUS 0x0C44
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#define REG_PA_SC_WINDOW_OFFSET 0x2080
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#define REG_PA_SC_WINDOW_SCISSOR_BR 0x2082
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#define REG_PA_SC_WINDOW_SCISSOR_TL 0x2081
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#define REG_PA_SU_FACE_DATA 0x0C86
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#define REG_PA_SU_POINT_SIZE 0x2280
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#define REG_PA_SU_LINE_CNTL 0x2282
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#define REG_PA_SU_POLY_OFFSET_BACK_OFFSET 0x2383
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#define REG_PA_SU_POLY_OFFSET_FRONT_SCALE 0x2380
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#define REG_PA_SU_SC_MODE_CNTL 0x2205
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#define REG_PC_INDEX_OFFSET 0x2102
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#define REG_RBBM_CNTL 0x003B
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#define REG_RBBM_INT_ACK 0x03B6
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#define REG_RBBM_INT_CNTL 0x03B4
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#define REG_RBBM_INT_STATUS 0x03B5
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#define REG_RBBM_PATCH_RELEASE 0x0001
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#define REG_RBBM_PERIPHID1 0x03F9
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#define REG_RBBM_PERIPHID2 0x03FA
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#define REG_RBBM_DEBUG 0x039B
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#define REG_RBBM_DEBUG_OUT 0x03A0
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#define REG_RBBM_DEBUG_CNTL 0x03A1
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||
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#define REG_RBBM_PM_OVERRIDE1 0x039C
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||
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#define REG_RBBM_PM_OVERRIDE2 0x039D
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||
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#define REG_RBBM_READ_ERROR 0x03B3
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||
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#define REG_RBBM_SOFT_RESET 0x003C
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||
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#define REG_RBBM_STATUS 0x05D0
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||
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||
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#define REG_RB_COLORCONTROL 0x2202
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#define REG_RB_COLOR_DEST_MASK 0x2326
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||
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#define REG_RB_COLOR_MASK 0x2104
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||
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#define REG_RB_COPY_CONTROL 0x2318
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||
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#define REG_RB_DEPTHCONTROL 0x2200
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||
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#define REG_RB_EDRAM_INFO 0x0F02
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||
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#define REG_RB_MODECONTROL 0x2208
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||
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#define REG_RB_SURFACE_INFO 0x2000
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||
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#define REG_RB_SAMPLE_POS 0x220a
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||
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||
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#define REG_SCRATCH_ADDR 0x01DD
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||
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#define REG_SCRATCH_REG0 0x0578
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||
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#define REG_SCRATCH_REG2 0x057A
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||
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#define REG_SCRATCH_UMSK 0x01DC
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||
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||
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#define REG_SQ_CF_BOOLEANS 0x4900
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||
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#define REG_SQ_CF_LOOP 0x4908
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||
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#define REG_SQ_GPR_MANAGEMENT 0x0D00
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||
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#define REG_SQ_FLOW_CONTROL 0x0D01
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||
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#define REG_SQ_INST_STORE_MANAGMENT 0x0D02
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||
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#define REG_SQ_INT_ACK 0x0D36
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||
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#define REG_SQ_INT_CNTL 0x0D34
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||
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#define REG_SQ_INT_STATUS 0x0D35
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||
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#define REG_SQ_PROGRAM_CNTL 0x2180
|
||
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|
#define REG_SQ_PS_PROGRAM 0x21F6
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||
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|
#define REG_SQ_VS_PROGRAM 0x21F7
|
||
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|
#define REG_SQ_WRAPPING_0 0x2183
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||
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|
#define REG_SQ_WRAPPING_1 0x2184
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||
|
|
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||
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|
#define REG_VGT_ENHANCE 0x2294
|
||
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|
#define REG_VGT_INDX_OFFSET 0x2102
|
||
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|
#define REG_VGT_MAX_VTX_INDX 0x2100
|
||
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|
#define REG_VGT_MIN_VTX_INDX 0x2101
|
||
|
|
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||
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|
#define REG_TP0_CHICKEN 0x0E1E
|
||
|
|
#define REG_TC_CNTL_STATUS 0x0E00
|
||
|
|
#define REG_PA_SC_AA_CONFIG 0x2301
|
||
|
|
#define REG_VGT_VERTEX_REUSE_BLOCK_CNTL 0x2316
|
||
|
|
#define REG_SQ_INTERPOLATOR_CNTL 0x2182
|
||
|
|
#define REG_RB_DEPTH_INFO 0x2002
|
||
|
|
#define REG_COHER_DEST_BASE_0 0x2006
|
||
|
|
#define REG_RB_FOG_COLOR 0x2109
|
||
|
|
#define REG_RB_STENCILREFMASK_BF 0x210C
|
||
|
|
#define REG_PA_SC_LINE_STIPPLE 0x2283
|
||
|
|
#define REG_SQ_PS_CONST 0x2308
|
||
|
|
#define REG_RB_DEPTH_CLEAR 0x231D
|
||
|
|
#define REG_RB_SAMPLE_COUNT_CTL 0x2324
|
||
|
|
#define REG_SQ_CONSTANT_0 0x4000
|
||
|
|
#define REG_SQ_FETCH_0 0x4800
|
||
|
|
|
||
|
|
#define REG_COHER_BASE_PM4 0xA2A
|
||
|
|
#define REG_COHER_STATUS_PM4 0xA2B
|
||
|
|
#define REG_COHER_SIZE_PM4 0xA29
|
||
|
|
|
||
|
|
/*registers added in adreno220*/
|
||
|
|
#define REG_A220_PC_INDX_OFFSET REG_VGT_INDX_OFFSET
|
||
|
|
#define REG_A220_PC_VERTEX_REUSE_BLOCK_CNTL REG_VGT_VERTEX_REUSE_BLOCK_CNTL
|
||
|
|
#define REG_A220_PC_MAX_VTX_INDX REG_VGT_MAX_VTX_INDX
|
||
|
|
#define REG_A220_RB_LRZ_VSC_CONTROL 0x2209
|
||
|
|
#define REG_A220_GRAS_CONTROL 0x2210
|
||
|
|
#define REG_A220_VSC_BIN_SIZE 0x0C01
|
||
|
|
#define REG_A220_VSC_PIPE_DATA_LENGTH_7 0x0C1D
|
||
|
|
|
||
|
|
/*registers added in adreno225*/
|
||
|
|
#define REG_A225_RB_COLOR_INFO3 0x2005
|
||
|
|
#define REG_A225_PC_MULTI_PRIM_IB_RESET_INDX 0x2103
|
||
|
|
#define REG_A225_GRAS_UCP0X 0x2340
|
||
|
|
#define REG_A225_GRAS_UCP5W 0x2357
|
||
|
|
#define REG_A225_GRAS_UCP_ENABLED 0x2360
|
||
|
|
|
||
|
|
/* Debug registers used by snapshot */
|
||
|
|
#define REG_PA_SU_DEBUG_CNTL 0x0C80
|
||
|
|
#define REG_PA_SU_DEBUG_DATA 0x0C81
|
||
|
|
#define REG_RB_DEBUG_CNTL 0x0F26
|
||
|
|
#define REG_RB_DEBUG_DATA 0x0F27
|
||
|
|
#define REG_PC_DEBUG_CNTL 0x0C38
|
||
|
|
#define REG_PC_DEBUG_DATA 0x0C39
|
||
|
|
#define REG_GRAS_DEBUG_CNTL 0x0C80
|
||
|
|
#define REG_GRAS_DEBUG_DATA 0x0C81
|
||
|
|
#define REG_SQ_DEBUG_MISC 0x0D05
|
||
|
|
#define REG_SQ_DEBUG_INPUT_FSM 0x0DAE
|
||
|
|
#define REG_SQ_DEBUG_CONST_MGR_FSM 0x0DAF
|
||
|
|
#define REG_SQ_DEBUG_EXP_ALLOC 0x0DB3
|
||
|
|
#define REG_SQ_DEBUG_FSM_ALU_0 0x0DB1
|
||
|
|
#define REG_SQ_DEBUG_FSM_ALU_1 0x0DB2
|
||
|
|
#define REG_SQ_DEBUG_PTR_BUFF 0x0DB4
|
||
|
|
#define REG_SQ_DEBUG_GPR_VTX 0x0DB5
|
||
|
|
#define REG_SQ_DEBUG_GPR_PIX 0x0DB6
|
||
|
|
#define REG_SQ_DEBUG_TB_STATUS_SEL 0x0DB7
|
||
|
|
#define REG_SQ_DEBUG_VTX_TB_0 0x0DB8
|
||
|
|
#define REG_SQ_DEBUG_VTX_TB_1 0x0DB9
|
||
|
|
#define REG_SQ_DEBUG_VTX_TB_STATE_MEM 0x0DBB
|
||
|
|
#define REG_SQ_DEBUG_TP_FSM 0x0DB0
|
||
|
|
#define REG_SQ_DEBUG_VTX_TB_STATUS_REG 0x0DBA
|
||
|
|
#define REG_SQ_DEBUG_PIX_TB_0 0x0DBC
|
||
|
|
#define REG_SQ_DEBUG_PIX_TB_STATUS_REG_0 0x0DBD
|
||
|
|
#define REG_SQ_DEBUG_PIX_TB_STATUS_REG_1 0x0DBE
|
||
|
|
#define REG_SQ_DEBUG_PIX_TB_STATUS_REG_2 0x0DBF
|
||
|
|
#define REG_SQ_DEBUG_PIX_TB_STATUS_REG_3 0x0DC0
|
||
|
|
#define REG_SQ_DEBUG_PIX_TB_STATE_MEM 0x0DC1
|
||
|
|
#define REG_SQ_DEBUG_MISC_0 0x2309
|
||
|
|
#define REG_SQ_DEBUG_MISC_1 0x230A
|
||
|
|
|
||
|
|
#endif /* __A200_REG_H */
|