88 lines
2.2 KiB
C
88 lines
2.2 KiB
C
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/*
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* arch/sh/include/asm/dma-sh.h
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*
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* Copyright (C) 2000 Takashi YOSHII
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* Copyright (C) 2003 Paul Mundt
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*/
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#ifndef __DMA_SH_H
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#define __DMA_SH_H
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#include <asm/dma-register.h>
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#include <cpu/dma-register.h>
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#include <cpu/dma.h>
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/* DMAOR contorl: The DMAOR access size is different by CPU.*/
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#if defined(CONFIG_CPU_SUBTYPE_SH7723) || \
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defined(CONFIG_CPU_SUBTYPE_SH7724) || \
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defined(CONFIG_CPU_SUBTYPE_SH7780) || \
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defined(CONFIG_CPU_SUBTYPE_SH7785)
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#define dmaor_read_reg(n) \
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(n ? __raw_readw(SH_DMAC_BASE1 + DMAOR) \
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: __raw_readw(SH_DMAC_BASE0 + DMAOR))
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#define dmaor_write_reg(n, data) \
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(n ? __raw_writew(data, SH_DMAC_BASE1 + DMAOR) \
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: __raw_writew(data, SH_DMAC_BASE0 + DMAOR))
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#else /* Other CPU */
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#define dmaor_read_reg(n) __raw_readw(SH_DMAC_BASE0 + DMAOR)
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#define dmaor_write_reg(n, data) __raw_writew(data, SH_DMAC_BASE0 + DMAOR)
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#endif
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static int dmte_irq_map[] __maybe_unused = {
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#if (MAX_DMA_CHANNELS >= 4)
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DMTE0_IRQ,
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DMTE0_IRQ + 1,
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DMTE0_IRQ + 2,
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DMTE0_IRQ + 3,
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#endif
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#if (MAX_DMA_CHANNELS >= 6)
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DMTE4_IRQ,
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DMTE4_IRQ + 1,
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#endif
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#if (MAX_DMA_CHANNELS >= 8)
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DMTE6_IRQ,
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DMTE6_IRQ + 1,
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#endif
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#if (MAX_DMA_CHANNELS >= 12)
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DMTE8_IRQ,
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DMTE9_IRQ,
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DMTE10_IRQ,
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DMTE11_IRQ,
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#endif
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};
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/*
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* Define the default configuration for dual address memory-memory transfer.
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* The 0x400 value represents auto-request, external->external.
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*/
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#define RS_DUAL (DM_INC | SM_INC | 0x400 | TS_INDEX2VAL(XMIT_SZ_32BIT))
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/* DMA base address */
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static u32 dma_base_addr[] __maybe_unused = {
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#if (MAX_DMA_CHANNELS >= 4)
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SH_DMAC_BASE0 + 0x00, /* channel 0 */
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SH_DMAC_BASE0 + 0x10,
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SH_DMAC_BASE0 + 0x20,
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SH_DMAC_BASE0 + 0x30,
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#endif
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#if (MAX_DMA_CHANNELS >= 6)
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SH_DMAC_BASE0 + 0x50,
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SH_DMAC_BASE0 + 0x60,
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#endif
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#if (MAX_DMA_CHANNELS >= 8)
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SH_DMAC_BASE1 + 0x00,
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SH_DMAC_BASE1 + 0x10,
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#endif
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#if (MAX_DMA_CHANNELS >= 12)
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SH_DMAC_BASE1 + 0x20,
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SH_DMAC_BASE1 + 0x30,
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SH_DMAC_BASE1 + 0x50,
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SH_DMAC_BASE1 + 0x60, /* channel 11 */
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#endif
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};
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#endif /* __DMA_SH_H */
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