265 lines
9.5 KiB
C
265 lines
9.5 KiB
C
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/*
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* Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights
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* reserved.
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*
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* This software is available to you under a choice of one of two
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* licenses. You may choose to be licensed under the terms of the GNU
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* General Public License (GPL) Version 2, available from the file
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* COPYING in the main directory of this source tree, or the NetLogic
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* license below:
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
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* BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
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* OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
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* IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef _ASM_NLM_XLR_PIC_H
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#define _ASM_NLM_XLR_PIC_H
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#define PIC_CLKS_PER_SEC 66666666ULL
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/* PIC hardware interrupt numbers */
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#define PIC_IRT_WD_INDEX 0
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#define PIC_IRT_TIMER_0_INDEX 1
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#define PIC_IRT_TIMER_1_INDEX 2
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#define PIC_IRT_TIMER_2_INDEX 3
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#define PIC_IRT_TIMER_3_INDEX 4
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#define PIC_IRT_TIMER_4_INDEX 5
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#define PIC_IRT_TIMER_5_INDEX 6
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#define PIC_IRT_TIMER_6_INDEX 7
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#define PIC_IRT_TIMER_7_INDEX 8
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#define PIC_IRT_CLOCK_INDEX PIC_IRT_TIMER_7_INDEX
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#define PIC_IRT_UART_0_INDEX 9
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#define PIC_IRT_UART_1_INDEX 10
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#define PIC_IRT_I2C_0_INDEX 11
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#define PIC_IRT_I2C_1_INDEX 12
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#define PIC_IRT_PCMCIA_INDEX 13
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#define PIC_IRT_GPIO_INDEX 14
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#define PIC_IRT_HYPER_INDEX 15
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#define PIC_IRT_PCIX_INDEX 16
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/* XLS */
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#define PIC_IRT_CDE_INDEX 15
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#define PIC_IRT_BRIDGE_TB_XLS_INDEX 16
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/* XLS */
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#define PIC_IRT_GMAC0_INDEX 17
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#define PIC_IRT_GMAC1_INDEX 18
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#define PIC_IRT_GMAC2_INDEX 19
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#define PIC_IRT_GMAC3_INDEX 20
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#define PIC_IRT_XGS0_INDEX 21
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#define PIC_IRT_XGS1_INDEX 22
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#define PIC_IRT_HYPER_FATAL_INDEX 23
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#define PIC_IRT_PCIX_FATAL_INDEX 24
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#define PIC_IRT_BRIDGE_AERR_INDEX 25
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#define PIC_IRT_BRIDGE_BERR_INDEX 26
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#define PIC_IRT_BRIDGE_TB_XLR_INDEX 27
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#define PIC_IRT_BRIDGE_AERR_NMI_INDEX 28
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/* XLS */
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#define PIC_IRT_GMAC4_INDEX 21
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#define PIC_IRT_GMAC5_INDEX 22
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#define PIC_IRT_GMAC6_INDEX 23
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#define PIC_IRT_GMAC7_INDEX 24
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#define PIC_IRT_BRIDGE_ERR_INDEX 25
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#define PIC_IRT_PCIE_LINK0_INDEX 26
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#define PIC_IRT_PCIE_LINK1_INDEX 27
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#define PIC_IRT_PCIE_LINK2_INDEX 23
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#define PIC_IRT_PCIE_LINK3_INDEX 24
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#define PIC_IRT_PCIE_XLSB0_LINK2_INDEX 28
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#define PIC_IRT_PCIE_XLSB0_LINK3_INDEX 29
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#define PIC_IRT_SRIO_LINK0_INDEX 26
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#define PIC_IRT_SRIO_LINK1_INDEX 27
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#define PIC_IRT_SRIO_LINK2_INDEX 28
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#define PIC_IRT_SRIO_LINK3_INDEX 29
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#define PIC_IRT_PCIE_INT_INDEX 28
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#define PIC_IRT_PCIE_FATAL_INDEX 29
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#define PIC_IRT_GPIO_B_INDEX 30
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#define PIC_IRT_USB_INDEX 31
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/* XLS */
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#define PIC_NUM_IRTS 32
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#define PIC_CLOCK_TIMER 7
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/* PIC Registers */
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#define PIC_CTRL 0x00
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#define PIC_IPI 0x04
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#define PIC_INT_ACK 0x06
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#define WD_MAX_VAL_0 0x08
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#define WD_MAX_VAL_1 0x09
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#define WD_MASK_0 0x0a
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#define WD_MASK_1 0x0b
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#define WD_HEARBEAT_0 0x0c
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#define WD_HEARBEAT_1 0x0d
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#define PIC_IRT_0_BASE 0x40
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#define PIC_IRT_1_BASE 0x80
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#define PIC_TIMER_MAXVAL_0_BASE 0x100
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#define PIC_TIMER_MAXVAL_1_BASE 0x110
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#define PIC_TIMER_COUNT_0_BASE 0x120
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#define PIC_TIMER_COUNT_1_BASE 0x130
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#define PIC_IRT_0(picintr) (PIC_IRT_0_BASE + (picintr))
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#define PIC_IRT_1(picintr) (PIC_IRT_1_BASE + (picintr))
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#define PIC_TIMER_MAXVAL_0(i) (PIC_TIMER_MAXVAL_0_BASE + (i))
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#define PIC_TIMER_MAXVAL_1(i) (PIC_TIMER_MAXVAL_1_BASE + (i))
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#define PIC_TIMER_COUNT_0(i) (PIC_TIMER_COUNT_0_BASE + (i))
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#define PIC_TIMER_COUNT_1(i) (PIC_TIMER_COUNT_0_BASE + (i))
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/*
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* Mapping between hardware interrupt numbers and IRQs on CPU
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* we use a simple scheme to map PIC interrupts 0-31 to IRQs
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* 8-39. This leaves the IRQ 0-7 for cpu interrupts like
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* count/compare and FMN
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*/
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#define PIC_IRQ_BASE 8
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#define PIC_INTR_TO_IRQ(i) (PIC_IRQ_BASE + (i))
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#define PIC_IRQ_TO_INTR(i) ((i) - PIC_IRQ_BASE)
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#define PIC_IRT_FIRST_IRQ PIC_IRQ_BASE
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#define PIC_WD_IRQ PIC_INTR_TO_IRQ(PIC_IRT_WD_INDEX)
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#define PIC_TIMER_0_IRQ PIC_INTR_TO_IRQ(PIC_IRT_TIMER_0_INDEX)
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#define PIC_TIMER_1_IRQ PIC_INTR_TO_IRQ(PIC_IRT_TIMER_1_INDEX)
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#define PIC_TIMER_2_IRQ PIC_INTR_TO_IRQ(PIC_IRT_TIMER_2_INDEX)
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#define PIC_TIMER_3_IRQ PIC_INTR_TO_IRQ(PIC_IRT_TIMER_3_INDEX)
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#define PIC_TIMER_4_IRQ PIC_INTR_TO_IRQ(PIC_IRT_TIMER_4_INDEX)
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#define PIC_TIMER_5_IRQ PIC_INTR_TO_IRQ(PIC_IRT_TIMER_5_INDEX)
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#define PIC_TIMER_6_IRQ PIC_INTR_TO_IRQ(PIC_IRT_TIMER_6_INDEX)
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#define PIC_TIMER_7_IRQ PIC_INTR_TO_IRQ(PIC_IRT_TIMER_7_INDEX)
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#define PIC_CLOCK_IRQ (PIC_TIMER_7_IRQ)
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#define PIC_UART_0_IRQ PIC_INTR_TO_IRQ(PIC_IRT_UART_0_INDEX)
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#define PIC_UART_1_IRQ PIC_INTR_TO_IRQ(PIC_IRT_UART_1_INDEX)
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#define PIC_I2C_0_IRQ PIC_INTR_TO_IRQ(PIC_IRT_I2C_0_INDEX)
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#define PIC_I2C_1_IRQ PIC_INTR_TO_IRQ(PIC_IRT_I2C_1_INDEX)
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#define PIC_PCMCIA_IRQ PIC_INTR_TO_IRQ(PIC_IRT_PCMCIA_INDEX)
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#define PIC_GPIO_IRQ PIC_INTR_TO_IRQ(PIC_IRT_GPIO_INDEX)
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#define PIC_HYPER_IRQ PIC_INTR_TO_IRQ(PIC_IRT_HYPER_INDEX)
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#define PIC_PCIX_IRQ PIC_INTR_TO_IRQ(PIC_IRT_PCIX_INDEX)
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/* XLS */
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#define PIC_CDE_IRQ PIC_INTR_TO_IRQ(PIC_IRT_CDE_INDEX)
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#define PIC_BRIDGE_TB_XLS_IRQ PIC_INTR_TO_IRQ(PIC_IRT_BRIDGE_TB_XLS_INDEX)
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/* end XLS */
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#define PIC_GMAC_0_IRQ PIC_INTR_TO_IRQ(PIC_IRT_GMAC0_INDEX)
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#define PIC_GMAC_1_IRQ PIC_INTR_TO_IRQ(PIC_IRT_GMAC1_INDEX)
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#define PIC_GMAC_2_IRQ PIC_INTR_TO_IRQ(PIC_IRT_GMAC2_INDEX)
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#define PIC_GMAC_3_IRQ PIC_INTR_TO_IRQ(PIC_IRT_GMAC3_INDEX)
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#define PIC_XGS_0_IRQ PIC_INTR_TO_IRQ(PIC_IRT_XGS0_INDEX)
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#define PIC_XGS_1_IRQ PIC_INTR_TO_IRQ(PIC_IRT_XGS1_INDEX)
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#define PIC_HYPER_FATAL_IRQ PIC_INTR_TO_IRQ(PIC_IRT_HYPER_FATAL_INDEX)
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#define PIC_PCIX_FATAL_IRQ PIC_INTR_TO_IRQ(PIC_IRT_PCIX_FATAL_INDEX)
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#define PIC_BRIDGE_AERR_IRQ PIC_INTR_TO_IRQ(PIC_IRT_BRIDGE_AERR_INDEX)
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#define PIC_BRIDGE_BERR_IRQ PIC_INTR_TO_IRQ(PIC_IRT_BRIDGE_BERR_INDEX)
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#define PIC_BRIDGE_TB_XLR_IRQ PIC_INTR_TO_IRQ(PIC_IRT_BRIDGE_TB_XLR_INDEX)
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#define PIC_BRIDGE_AERR_NMI_IRQ PIC_INTR_TO_IRQ(PIC_IRT_BRIDGE_AERR_NMI_INDEX)
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/* XLS defines */
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#define PIC_GMAC_4_IRQ PIC_INTR_TO_IRQ(PIC_IRT_GMAC4_INDEX)
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#define PIC_GMAC_5_IRQ PIC_INTR_TO_IRQ(PIC_IRT_GMAC5_INDEX)
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#define PIC_GMAC_6_IRQ PIC_INTR_TO_IRQ(PIC_IRT_GMAC6_INDEX)
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#define PIC_GMAC_7_IRQ PIC_INTR_TO_IRQ(PIC_IRT_GMAC7_INDEX)
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#define PIC_BRIDGE_ERR_IRQ PIC_INTR_TO_IRQ(PIC_IRT_BRIDGE_ERR_INDEX)
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#define PIC_PCIE_LINK0_IRQ PIC_INTR_TO_IRQ(PIC_IRT_PCIE_LINK0_INDEX)
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#define PIC_PCIE_LINK1_IRQ PIC_INTR_TO_IRQ(PIC_IRT_PCIE_LINK1_INDEX)
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#define PIC_PCIE_LINK2_IRQ PIC_INTR_TO_IRQ(PIC_IRT_PCIE_LINK2_INDEX)
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#define PIC_PCIE_LINK3_IRQ PIC_INTR_TO_IRQ(PIC_IRT_PCIE_LINK3_INDEX)
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#define PIC_PCIE_XLSB0_LINK2_IRQ PIC_INTR_TO_IRQ(PIC_IRT_PCIE_XLSB0_LINK2_INDEX)
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#define PIC_PCIE_XLSB0_LINK3_IRQ PIC_INTR_TO_IRQ(PIC_IRT_PCIE_XLSB0_LINK3_INDEX)
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#define PIC_SRIO_LINK0_IRQ PIC_INTR_TO_IRQ(PIC_IRT_SRIO_LINK0_INDEX)
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#define PIC_SRIO_LINK1_IRQ PIC_INTR_TO_IRQ(PIC_IRT_SRIO_LINK1_INDEX)
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#define PIC_SRIO_LINK2_IRQ PIC_INTR_TO_IRQ(PIC_IRT_SRIO_LINK2_INDEX)
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#define PIC_SRIO_LINK3_IRQ PIC_INTR_TO_IRQ(PIC_IRT_SRIO_LINK3_INDEX)
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#define PIC_PCIE_INT_IRQ PIC_INTR_TO_IRQ(PIC_IRT_PCIE_INT__INDEX)
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#define PIC_PCIE_FATAL_IRQ PIC_INTR_TO_IRQ(PIC_IRT_PCIE_FATAL_INDEX)
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#define PIC_GPIO_B_IRQ PIC_INTR_TO_IRQ(PIC_IRT_GPIO_B_INDEX)
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#define PIC_USB_IRQ PIC_INTR_TO_IRQ(PIC_IRT_USB_INDEX)
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#define PIC_IRT_LAST_IRQ PIC_USB_IRQ
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/* end XLS */
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#ifndef __ASSEMBLY__
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#define PIC_IRQ_IS_EDGE_TRIGGERED(irq) (((irq) >= PIC_TIMER_0_IRQ) && \
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((irq) <= PIC_TIMER_7_IRQ))
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#define PIC_IRQ_IS_IRT(irq) (((irq) >= PIC_IRT_FIRST_IRQ) && \
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((irq) <= PIC_IRT_LAST_IRQ))
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static inline int
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nlm_irq_to_irt(int irq)
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{
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if (PIC_IRQ_IS_IRT(irq) == 0)
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return -1;
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return PIC_IRQ_TO_INTR(irq);
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}
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static inline int
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nlm_irt_to_irq(int irt)
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{
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return PIC_INTR_TO_IRQ(irt);
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}
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static inline void
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nlm_pic_enable_irt(uint64_t base, int irt)
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{
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uint32_t reg;
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reg = nlm_read_reg(base, PIC_IRT_1(irt));
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nlm_write_reg(base, PIC_IRT_1(irt), reg | (1u << 31));
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}
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static inline void
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nlm_pic_disable_irt(uint64_t base, int irt)
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{
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uint32_t reg;
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reg = nlm_read_reg(base, PIC_IRT_1(irt));
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nlm_write_reg(base, PIC_IRT_1(irt), reg & ~(1u << 31));
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}
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static inline void
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nlm_pic_send_ipi(uint64_t base, int hwt, int irq, int nmi)
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{
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unsigned int tid, pid;
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tid = hwt & 0x3;
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pid = (hwt >> 2) & 0x07;
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nlm_write_reg(base, PIC_IPI,
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(pid << 20) | (tid << 16) | (nmi << 8) | irq);
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}
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static inline void
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nlm_pic_ack(uint64_t base, int irt)
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{
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nlm_write_reg(base, PIC_INT_ACK, 1u << irt);
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}
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static inline void
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nlm_pic_init_irt(uint64_t base, int irt, int irq, int hwt)
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{
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nlm_write_reg(base, PIC_IRT_0(irt), (1u << hwt));
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/* local scheduling, invalid, level by default */
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nlm_write_reg(base, PIC_IRT_1(irt),
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(1 << 30) | (1 << 6) | irq);
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}
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extern uint64_t nlm_pic_base;
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#endif
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#endif /* _ASM_NLM_XLR_PIC_H */
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