367 lines
10 KiB
C
367 lines
10 KiB
C
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/*
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* OMAP Voltage Controller (VC) interface
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*
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* Copyright (C) 2011 Texas Instruments, Inc.
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*/
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#include <linux/kernel.h>
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#include <linux/delay.h>
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#include <linux/init.h>
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#include <linux/bug.h>
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#include <plat/cpu.h>
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#include "voltage.h"
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#include "vc.h"
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#include "prm-regbits-34xx.h"
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#include "prm-regbits-44xx.h"
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#include "prm44xx.h"
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/**
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* struct omap_vc_channel_cfg - describe the cfg_channel bitfield
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* @sa: bit for slave address
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* @rav: bit for voltage configuration register
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* @rac: bit for command configuration register
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* @racen: enable bit for RAC
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* @cmd: bit for command value set selection
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*
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* Channel configuration bits, common for OMAP3+
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* OMAP3 register: PRM_VC_CH_CONF
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* OMAP4 register: PRM_VC_CFG_CHANNEL
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* OMAP5 register: PRM_VC_SMPS_<voltdm>_CONFIG
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*/
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struct omap_vc_channel_cfg {
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u8 sa;
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u8 rav;
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u8 rac;
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u8 racen;
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u8 cmd;
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};
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static struct omap_vc_channel_cfg vc_default_channel_cfg = {
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.sa = BIT(0),
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.rav = BIT(1),
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.rac = BIT(2),
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.racen = BIT(3),
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.cmd = BIT(4),
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};
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/*
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* On OMAP3+, all VC channels have the above default bitfield
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* configuration, except the OMAP4 MPU channel. This appears
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* to be a freak accident as every other VC channel has the
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* default configuration, thus creating a mutant channel config.
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*/
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static struct omap_vc_channel_cfg vc_mutant_channel_cfg = {
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.sa = BIT(0),
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.rav = BIT(2),
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.rac = BIT(3),
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.racen = BIT(4),
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.cmd = BIT(1),
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};
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static struct omap_vc_channel_cfg *vc_cfg_bits;
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#define CFG_CHANNEL_MASK 0x1f
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/**
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* omap_vc_config_channel - configure VC channel to PMIC mappings
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* @voltdm: pointer to voltagdomain defining the desired VC channel
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*
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* Configures the VC channel to PMIC mappings for the following
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* PMIC settings
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* - i2c slave address (SA)
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* - voltage configuration address (RAV)
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* - command configuration address (RAC) and enable bit (RACEN)
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* - command values for ON, ONLP, RET and OFF (CMD)
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*
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* This function currently only allows flexible configuration of the
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* non-default channel. Starting with OMAP4, there are more than 2
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* channels, with one defined as the default (on OMAP4, it's MPU.)
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* Only the non-default channel can be configured.
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*/
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static int omap_vc_config_channel(struct voltagedomain *voltdm)
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{
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struct omap_vc_channel *vc = voltdm->vc;
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/*
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* For default channel, the only configurable bit is RACEN.
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* All others must stay at zero (see function comment above.)
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*/
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if (vc->flags & OMAP_VC_CHANNEL_DEFAULT)
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vc->cfg_channel &= vc_cfg_bits->racen;
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voltdm->rmw(CFG_CHANNEL_MASK << vc->cfg_channel_sa_shift,
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vc->cfg_channel << vc->cfg_channel_sa_shift,
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vc->cfg_channel_reg);
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return 0;
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}
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/* Voltage scale and accessory APIs */
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int omap_vc_pre_scale(struct voltagedomain *voltdm,
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unsigned long target_volt,
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u8 *target_vsel, u8 *current_vsel)
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{
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struct omap_vc_channel *vc = voltdm->vc;
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u32 vc_cmdval;
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/* Check if sufficient pmic info is available for this vdd */
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if (!voltdm->pmic) {
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pr_err("%s: Insufficient pmic info to scale the vdd_%s\n",
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__func__, voltdm->name);
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return -EINVAL;
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}
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if (!voltdm->pmic->uv_to_vsel) {
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pr_err("%s: PMIC function to convert voltage in uV to"
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"vsel not registered. Hence unable to scale voltage"
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"for vdd_%s\n", __func__, voltdm->name);
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return -ENODATA;
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}
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if (!voltdm->read || !voltdm->write) {
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pr_err("%s: No read/write API for accessing vdd_%s regs\n",
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__func__, voltdm->name);
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return -EINVAL;
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}
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*target_vsel = voltdm->pmic->uv_to_vsel(target_volt);
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*current_vsel = voltdm->pmic->uv_to_vsel(voltdm->nominal_volt);
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/* Setting the ON voltage to the new target voltage */
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vc_cmdval = voltdm->read(vc->cmdval_reg);
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vc_cmdval &= ~vc->common->cmd_on_mask;
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vc_cmdval |= (*target_vsel << vc->common->cmd_on_shift);
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voltdm->write(vc_cmdval, vc->cmdval_reg);
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omap_vp_update_errorgain(voltdm, target_volt);
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return 0;
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}
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void omap_vc_post_scale(struct voltagedomain *voltdm,
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unsigned long target_volt,
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u8 target_vsel, u8 current_vsel)
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{
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u32 smps_steps = 0, smps_delay = 0;
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smps_steps = abs(target_vsel - current_vsel);
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/* SMPS slew rate / step size. 2us added as buffer. */
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smps_delay = ((smps_steps * voltdm->pmic->step_size) /
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voltdm->pmic->slew_rate) + 2;
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udelay(smps_delay);
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}
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/* vc_bypass_scale - VC bypass method of voltage scaling */
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int omap_vc_bypass_scale(struct voltagedomain *voltdm,
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unsigned long target_volt)
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{
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struct omap_vc_channel *vc = voltdm->vc;
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u32 loop_cnt = 0, retries_cnt = 0;
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u32 vc_valid, vc_bypass_val_reg, vc_bypass_value;
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u8 target_vsel, current_vsel;
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int ret;
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ret = omap_vc_pre_scale(voltdm, target_volt, &target_vsel, ¤t_vsel);
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if (ret)
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return ret;
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vc_valid = vc->common->valid;
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vc_bypass_val_reg = vc->common->bypass_val_reg;
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vc_bypass_value = (target_vsel << vc->common->data_shift) |
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(vc->volt_reg_addr << vc->common->regaddr_shift) |
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(vc->i2c_slave_addr << vc->common->slaveaddr_shift);
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voltdm->write(vc_bypass_value, vc_bypass_val_reg);
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voltdm->write(vc_bypass_value | vc_valid, vc_bypass_val_reg);
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vc_bypass_value = voltdm->read(vc_bypass_val_reg);
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/*
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* Loop till the bypass command is acknowledged from the SMPS.
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* NOTE: This is legacy code. The loop count and retry count needs
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* to be revisited.
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*/
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while (!(vc_bypass_value & vc_valid)) {
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loop_cnt++;
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if (retries_cnt > 10) {
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pr_warning("%s: Retry count exceeded\n", __func__);
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return -ETIMEDOUT;
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}
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if (loop_cnt > 50) {
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retries_cnt++;
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loop_cnt = 0;
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udelay(10);
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}
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vc_bypass_value = voltdm->read(vc_bypass_val_reg);
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}
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omap_vc_post_scale(voltdm, target_volt, target_vsel, current_vsel);
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return 0;
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}
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static void __init omap3_vfsm_init(struct voltagedomain *voltdm)
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{
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/*
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* Voltage Manager FSM parameters init
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* XXX This data should be passed in from the board file
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*/
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voltdm->write(OMAP3_CLKSETUP, OMAP3_PRM_CLKSETUP_OFFSET);
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voltdm->write(OMAP3_VOLTOFFSET, OMAP3_PRM_VOLTOFFSET_OFFSET);
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voltdm->write(OMAP3_VOLTSETUP2, OMAP3_PRM_VOLTSETUP2_OFFSET);
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}
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static void __init omap3_vc_init_channel(struct voltagedomain *voltdm)
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{
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static bool is_initialized;
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if (is_initialized)
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return;
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omap3_vfsm_init(voltdm);
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is_initialized = true;
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}
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/* OMAP4 specific voltage init functions */
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static void __init omap4_vc_init_channel(struct voltagedomain *voltdm)
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{
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static bool is_initialized;
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u32 vc_val;
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if (is_initialized)
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return;
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/* XXX These are magic numbers and do not belong! */
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vc_val = (0x60 << OMAP4430_SCLL_SHIFT | 0x26 << OMAP4430_SCLH_SHIFT);
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voltdm->write(vc_val, OMAP4_PRM_VC_CFG_I2C_CLK_OFFSET);
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is_initialized = true;
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}
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/**
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* omap_vc_i2c_init - initialize I2C interface to PMIC
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* @voltdm: voltage domain containing VC data
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*
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* Use PMIC supplied settings for I2C high-speed mode and
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* master code (if set) and program the VC I2C configuration
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* register.
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*
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* The VC I2C configuration is common to all VC channels,
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* so this function only configures I2C for the first VC
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* channel registers. All other VC channels will use the
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* same configuration.
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*/
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static void __init omap_vc_i2c_init(struct voltagedomain *voltdm)
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{
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struct omap_vc_channel *vc = voltdm->vc;
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static bool initialized;
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static bool i2c_high_speed;
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u8 mcode;
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if (initialized) {
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if (voltdm->pmic->i2c_high_speed != i2c_high_speed)
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pr_warn("%s: I2C config for vdd_%s does not match other channels (%u).",
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__func__, voltdm->name, i2c_high_speed);
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return;
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}
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i2c_high_speed = voltdm->pmic->i2c_high_speed;
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if (i2c_high_speed)
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voltdm->rmw(vc->common->i2c_cfg_hsen_mask,
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vc->common->i2c_cfg_hsen_mask,
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vc->common->i2c_cfg_reg);
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mcode = voltdm->pmic->i2c_mcode;
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if (mcode)
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voltdm->rmw(vc->common->i2c_mcode_mask,
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mcode << __ffs(vc->common->i2c_mcode_mask),
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vc->common->i2c_cfg_reg);
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initialized = true;
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}
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void __init omap_vc_init_channel(struct voltagedomain *voltdm)
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{
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struct omap_vc_channel *vc = voltdm->vc;
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u8 on_vsel, onlp_vsel, ret_vsel, off_vsel;
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u32 val;
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if (!voltdm->pmic || !voltdm->pmic->uv_to_vsel) {
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pr_err("%s: No PMIC info for vdd_%s\n", __func__, voltdm->name);
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return;
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}
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if (!voltdm->read || !voltdm->write) {
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pr_err("%s: No read/write API for accessing vdd_%s regs\n",
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__func__, voltdm->name);
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return;
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}
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vc->cfg_channel = 0;
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if (vc->flags & OMAP_VC_CHANNEL_CFG_MUTANT)
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vc_cfg_bits = &vc_mutant_channel_cfg;
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else
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vc_cfg_bits = &vc_default_channel_cfg;
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/* get PMIC/board specific settings */
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vc->i2c_slave_addr = voltdm->pmic->i2c_slave_addr;
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vc->volt_reg_addr = voltdm->pmic->volt_reg_addr;
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vc->cmd_reg_addr = voltdm->pmic->cmd_reg_addr;
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vc->setup_time = voltdm->pmic->volt_setup_time;
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/* Configure the i2c slave address for this VC */
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voltdm->rmw(vc->smps_sa_mask,
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vc->i2c_slave_addr << __ffs(vc->smps_sa_mask),
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vc->smps_sa_reg);
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vc->cfg_channel |= vc_cfg_bits->sa;
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/*
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* Configure the PMIC register addresses.
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*/
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voltdm->rmw(vc->smps_volra_mask,
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vc->volt_reg_addr << __ffs(vc->smps_volra_mask),
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vc->smps_volra_reg);
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vc->cfg_channel |= vc_cfg_bits->rav;
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if (vc->cmd_reg_addr) {
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voltdm->rmw(vc->smps_cmdra_mask,
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vc->cmd_reg_addr << __ffs(vc->smps_cmdra_mask),
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vc->smps_cmdra_reg);
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vc->cfg_channel |= vc_cfg_bits->rac | vc_cfg_bits->racen;
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}
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/* Set up the on, inactive, retention and off voltage */
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on_vsel = voltdm->pmic->uv_to_vsel(voltdm->pmic->on_volt);
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onlp_vsel = voltdm->pmic->uv_to_vsel(voltdm->pmic->onlp_volt);
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ret_vsel = voltdm->pmic->uv_to_vsel(voltdm->pmic->ret_volt);
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off_vsel = voltdm->pmic->uv_to_vsel(voltdm->pmic->off_volt);
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val = ((on_vsel << vc->common->cmd_on_shift) |
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(onlp_vsel << vc->common->cmd_onlp_shift) |
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(ret_vsel << vc->common->cmd_ret_shift) |
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(off_vsel << vc->common->cmd_off_shift));
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|
|
voltdm->write(val, vc->cmdval_reg);
|
||
|
|
vc->cfg_channel |= vc_cfg_bits->cmd;
|
||
|
|
|
||
|
|
/* Channel configuration */
|
||
|
|
omap_vc_config_channel(voltdm);
|
||
|
|
|
||
|
|
/* Configure the setup times */
|
||
|
|
voltdm->rmw(voltdm->vfsm->voltsetup_mask,
|
||
|
|
vc->setup_time << __ffs(voltdm->vfsm->voltsetup_mask),
|
||
|
|
voltdm->vfsm->voltsetup_reg);
|
||
|
|
|
||
|
|
omap_vc_i2c_init(voltdm);
|
||
|
|
|
||
|
|
if (cpu_is_omap34xx())
|
||
|
|
omap3_vc_init_channel(voltdm);
|
||
|
|
else if (cpu_is_omap44xx())
|
||
|
|
omap4_vc_init_channel(voltdm);
|
||
|
|
}
|
||
|
|
|