320 lines
8.6 KiB
C
320 lines
8.6 KiB
C
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/*
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* OMAP2+ common Power & Reset Management (PRM) IP block functions
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*
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* Copyright (C) 2011 Texas Instruments, Inc.
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* Tero Kristo <t-kristo@ti.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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*
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* For historical purposes, the API used to configure the PRM
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* interrupt handler refers to it as the "PRCM interrupt." The
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* underlying registers are located in the PRM on OMAP3/4.
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*
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* XXX This code should eventually be moved to a PRM driver.
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*/
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/init.h>
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#include <linux/io.h>
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#include <linux/irq.h>
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#include <linux/interrupt.h>
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#include <linux/slab.h>
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#include <plat/common.h>
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#include <plat/prcm.h>
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#include <plat/irqs.h>
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#include "prm2xxx_3xxx.h"
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#include "prm44xx.h"
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/*
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* OMAP_PRCM_MAX_NR_PENDING_REG: maximum number of PRM_IRQ*_MPU regs
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* XXX this is technically not needed, since
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* omap_prcm_register_chain_handler() could allocate this based on the
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* actual amount of memory needed for the SoC
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*/
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#define OMAP_PRCM_MAX_NR_PENDING_REG 2
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/*
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* prcm_irq_chips: an array of all of the "generic IRQ chips" in use
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* by the PRCM interrupt handler code. There will be one 'chip' per
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* PRM_{IRQSTATUS,IRQENABLE}_MPU register pair. (So OMAP3 will have
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* one "chip" and OMAP4 will have two.)
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*/
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static struct irq_chip_generic **prcm_irq_chips;
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/*
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* prcm_irq_setup: the PRCM IRQ parameters for the hardware the code
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* is currently running on. Defined and passed by initialization code
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* that calls omap_prcm_register_chain_handler().
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*/
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static struct omap_prcm_irq_setup *prcm_irq_setup;
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/* Private functions */
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/*
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* Move priority events from events to priority_events array
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*/
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static void omap_prcm_events_filter_priority(unsigned long *events,
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unsigned long *priority_events)
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{
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int i;
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for (i = 0; i < prcm_irq_setup->nr_regs; i++) {
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priority_events[i] =
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events[i] & prcm_irq_setup->priority_mask[i];
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events[i] ^= priority_events[i];
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}
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}
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/*
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* PRCM Interrupt Handler
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*
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* This is a common handler for the OMAP PRCM interrupts. Pending
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* interrupts are detected by a call to prcm_pending_events and
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* dispatched accordingly. Clearing of the wakeup events should be
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* done by the SoC specific individual handlers.
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*/
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static void omap_prcm_irq_handler(unsigned int irq, struct irq_desc *desc)
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{
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unsigned long pending[OMAP_PRCM_MAX_NR_PENDING_REG];
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unsigned long priority_pending[OMAP_PRCM_MAX_NR_PENDING_REG];
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struct irq_chip *chip = irq_desc_get_chip(desc);
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unsigned int virtirq;
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int nr_irqs = prcm_irq_setup->nr_regs * 32;
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/*
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* If we are suspended, mask all interrupts from PRCM level,
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* this does not ack them, and they will be pending until we
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* re-enable the interrupts, at which point the
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* omap_prcm_irq_handler will be executed again. The
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* _save_and_clear_irqen() function must ensure that the PRM
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* write to disable all IRQs has reached the PRM before
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* returning, or spurious PRCM interrupts may occur during
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* suspend.
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*/
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if (prcm_irq_setup->suspended) {
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prcm_irq_setup->save_and_clear_irqen(prcm_irq_setup->saved_mask);
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prcm_irq_setup->suspend_save_flag = true;
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}
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/*
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* Loop until all pending irqs are handled, since
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* generic_handle_irq() can cause new irqs to come
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*/
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while (!prcm_irq_setup->suspended) {
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prcm_irq_setup->read_pending_irqs(pending);
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/* No bit set, then all IRQs are handled */
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if (find_first_bit(pending, nr_irqs) >= nr_irqs)
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break;
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omap_prcm_events_filter_priority(pending, priority_pending);
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/*
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* Loop on all currently pending irqs so that new irqs
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* cannot starve previously pending irqs
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*/
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/* Serve priority events first */
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for_each_set_bit(virtirq, priority_pending, nr_irqs)
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generic_handle_irq(prcm_irq_setup->base_irq + virtirq);
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/* Serve normal events next */
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for_each_set_bit(virtirq, pending, nr_irqs)
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generic_handle_irq(prcm_irq_setup->base_irq + virtirq);
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}
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if (chip->irq_ack)
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chip->irq_ack(&desc->irq_data);
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if (chip->irq_eoi)
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chip->irq_eoi(&desc->irq_data);
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chip->irq_unmask(&desc->irq_data);
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prcm_irq_setup->ocp_barrier(); /* avoid spurious IRQs */
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}
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/* Public functions */
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/**
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* omap_prcm_event_to_irq - given a PRCM event name, returns the
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* corresponding IRQ on which the handler should be registered
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* @name: name of the PRCM interrupt bit to look up - see struct omap_prcm_irq
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*
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* Returns the Linux internal IRQ ID corresponding to @name upon success,
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* or -ENOENT upon failure.
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*/
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int omap_prcm_event_to_irq(const char *name)
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{
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int i;
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if (!prcm_irq_setup || !name)
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return -ENOENT;
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for (i = 0; i < prcm_irq_setup->nr_irqs; i++)
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if (!strcmp(prcm_irq_setup->irqs[i].name, name))
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return prcm_irq_setup->base_irq +
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prcm_irq_setup->irqs[i].offset;
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return -ENOENT;
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}
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/**
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* omap_prcm_irq_cleanup - reverses memory allocated and other steps
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* done by omap_prcm_register_chain_handler()
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*
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* No return value.
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*/
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void omap_prcm_irq_cleanup(void)
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{
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int i;
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if (!prcm_irq_setup) {
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pr_err("PRCM: IRQ handler not initialized; cannot cleanup\n");
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return;
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}
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if (prcm_irq_chips) {
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for (i = 0; i < prcm_irq_setup->nr_regs; i++) {
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if (prcm_irq_chips[i])
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irq_remove_generic_chip(prcm_irq_chips[i],
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0xffffffff, 0, 0);
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prcm_irq_chips[i] = NULL;
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}
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kfree(prcm_irq_chips);
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prcm_irq_chips = NULL;
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}
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kfree(prcm_irq_setup->saved_mask);
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prcm_irq_setup->saved_mask = NULL;
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kfree(prcm_irq_setup->priority_mask);
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prcm_irq_setup->priority_mask = NULL;
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irq_set_chained_handler(prcm_irq_setup->irq, NULL);
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if (prcm_irq_setup->base_irq > 0)
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irq_free_descs(prcm_irq_setup->base_irq,
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prcm_irq_setup->nr_regs * 32);
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prcm_irq_setup->base_irq = 0;
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}
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void omap_prcm_irq_prepare(void)
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{
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prcm_irq_setup->suspended = true;
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}
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void omap_prcm_irq_complete(void)
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{
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prcm_irq_setup->suspended = false;
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/* If we have not saved the masks, do not attempt to restore */
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if (!prcm_irq_setup->suspend_save_flag)
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return;
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prcm_irq_setup->suspend_save_flag = false;
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/*
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* Re-enable all masked PRCM irq sources, this causes the PRCM
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* interrupt to fire immediately if the events were masked
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* previously in the chain handler
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*/
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prcm_irq_setup->restore_irqen(prcm_irq_setup->saved_mask);
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}
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/**
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* omap_prcm_register_chain_handler - initializes the prcm chained interrupt
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* handler based on provided parameters
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* @irq_setup: hardware data about the underlying PRM/PRCM
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*
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* Set up the PRCM chained interrupt handler on the PRCM IRQ. Sets up
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* one generic IRQ chip per PRM interrupt status/enable register pair.
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* Returns 0 upon success, -EINVAL if called twice or if invalid
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* arguments are passed, or -ENOMEM on any other error.
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*/
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int omap_prcm_register_chain_handler(struct omap_prcm_irq_setup *irq_setup)
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{
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int nr_regs = irq_setup->nr_regs;
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u32 mask[OMAP_PRCM_MAX_NR_PENDING_REG];
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int offset, i;
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struct irq_chip_generic *gc;
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struct irq_chip_type *ct;
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if (!irq_setup)
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return -EINVAL;
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if (prcm_irq_setup) {
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pr_err("PRCM: already initialized; won't reinitialize\n");
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return -EINVAL;
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}
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if (nr_regs > OMAP_PRCM_MAX_NR_PENDING_REG) {
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pr_err("PRCM: nr_regs too large\n");
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return -EINVAL;
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}
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prcm_irq_setup = irq_setup;
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prcm_irq_chips = kzalloc(sizeof(void *) * nr_regs, GFP_KERNEL);
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prcm_irq_setup->saved_mask = kzalloc(sizeof(u32) * nr_regs, GFP_KERNEL);
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prcm_irq_setup->priority_mask = kzalloc(sizeof(u32) * nr_regs,
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GFP_KERNEL);
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if (!prcm_irq_chips || !prcm_irq_setup->saved_mask ||
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!prcm_irq_setup->priority_mask) {
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pr_err("PRCM: kzalloc failed\n");
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goto err;
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}
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memset(mask, 0, sizeof(mask));
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for (i = 0; i < irq_setup->nr_irqs; i++) {
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offset = irq_setup->irqs[i].offset;
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mask[offset >> 5] |= 1 << (offset & 0x1f);
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if (irq_setup->irqs[i].priority)
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irq_setup->priority_mask[offset >> 5] |=
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1 << (offset & 0x1f);
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}
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irq_set_chained_handler(irq_setup->irq, omap_prcm_irq_handler);
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irq_setup->base_irq = irq_alloc_descs(-1, 0, irq_setup->nr_regs * 32,
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0);
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if (irq_setup->base_irq < 0) {
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pr_err("PRCM: failed to allocate irq descs: %d\n",
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irq_setup->base_irq);
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goto err;
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}
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for (i = 0; i < irq_setup->nr_regs; i++) {
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gc = irq_alloc_generic_chip("PRCM", 1,
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irq_setup->base_irq + i * 32, prm_base,
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handle_level_irq);
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if (!gc) {
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pr_err("PRCM: failed to allocate generic chip\n");
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goto err;
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}
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ct = gc->chip_types;
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ct->chip.irq_ack = irq_gc_ack_set_bit;
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ct->chip.irq_mask = irq_gc_mask_clr_bit;
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ct->chip.irq_unmask = irq_gc_mask_set_bit;
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ct->regs.ack = irq_setup->ack + i * 4;
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ct->regs.mask = irq_setup->mask + i * 4;
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irq_setup_generic_chip(gc, mask[i], 0, IRQ_NOREQUEST, 0);
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prcm_irq_chips[i] = gc;
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}
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return 0;
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err:
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omap_prcm_irq_cleanup();
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return -ENOMEM;
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}
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