309 lines
8.3 KiB
C
309 lines
8.3 KiB
C
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/* Copyright (c) 2010-2012, The Linux Foundation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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* only version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*/
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#include <linux/module.h>
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#include <linux/kernel.h>
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#include <linux/delay.h>
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#include <linux/init.h>
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#include <linux/io.h>
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#include <mach/msm_iomap.h>
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#include "spm.h"
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enum {
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MSM_SPM_DEBUG_SHADOW = 1U << 0,
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MSM_SPM_DEBUG_VCTL = 1U << 1,
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};
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static int msm_spm_debug_mask;
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module_param_named(
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debug_mask, msm_spm_debug_mask, int, S_IRUGO | S_IWUSR | S_IWGRP
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);
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#define MSM_SPM_PMIC_STATE_IDLE 0
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static uint32_t msm_spm_reg_offsets[MSM_SPM_REG_NR] = {
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[MSM_SPM_REG_SAW_AVS_CTL] = 0x04,
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[MSM_SPM_REG_SAW_VCTL] = 0x08,
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[MSM_SPM_REG_SAW_STS] = 0x0C,
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[MSM_SPM_REG_SAW_CFG] = 0x10,
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[MSM_SPM_REG_SAW_SPM_CTL] = 0x14,
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[MSM_SPM_REG_SAW_SPM_SLP_TMR_DLY] = 0x18,
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[MSM_SPM_REG_SAW_SPM_WAKE_TMR_DLY] = 0x1C,
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[MSM_SPM_REG_SAW_SPM_PMIC_CTL] = 0x20,
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[MSM_SPM_REG_SAW_SLP_CLK_EN] = 0x24,
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[MSM_SPM_REG_SAW_SLP_HSFS_PRECLMP_EN] = 0x28,
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[MSM_SPM_REG_SAW_SLP_HSFS_POSTCLMP_EN] = 0x2C,
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[MSM_SPM_REG_SAW_SLP_CLMP_EN] = 0x30,
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[MSM_SPM_REG_SAW_SLP_RST_EN] = 0x34,
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[MSM_SPM_REG_SAW_SPM_MPM_CFG] = 0x38,
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};
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struct msm_spm_device {
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void __iomem *reg_base_addr;
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uint32_t reg_shadow[MSM_SPM_REG_NR];
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uint8_t awake_vlevel;
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uint8_t retention_vlevel;
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uint8_t collapse_vlevel;
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uint8_t retention_mid_vlevel;
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uint8_t collapse_mid_vlevel;
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uint32_t vctl_timeout_us;
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unsigned int low_power_mode;
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bool notify_rpm;
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bool dirty;
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};
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static DEFINE_PER_CPU_SHARED_ALIGNED(struct msm_spm_device, msm_spm_devices);
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/******************************************************************************
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* Internal helper functions
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*****************************************************************************/
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static inline void msm_spm_set_vctl(
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struct msm_spm_device *dev, uint32_t vlevel)
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{
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dev->reg_shadow[MSM_SPM_REG_SAW_VCTL] &= ~0xFF;
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dev->reg_shadow[MSM_SPM_REG_SAW_VCTL] |= vlevel;
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}
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static inline void msm_spm_set_spm_ctl(struct msm_spm_device *dev,
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uint32_t rpm_bypass, uint32_t mode_encoding)
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{
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dev->reg_shadow[MSM_SPM_REG_SAW_SPM_CTL] &= ~0x0F;
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dev->reg_shadow[MSM_SPM_REG_SAW_SPM_CTL] |= rpm_bypass << 3;
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dev->reg_shadow[MSM_SPM_REG_SAW_SPM_CTL] |= mode_encoding;
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}
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static inline void msm_spm_set_pmic_ctl(struct msm_spm_device *dev,
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uint32_t awake_vlevel, uint32_t mid_vlevel, uint32_t sleep_vlevel)
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{
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dev->reg_shadow[MSM_SPM_REG_SAW_SPM_PMIC_CTL] =
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(mid_vlevel << 16) | (awake_vlevel << 8) | (sleep_vlevel);
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}
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static inline void msm_spm_set_slp_rst_en(
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struct msm_spm_device *dev, uint32_t slp_rst_en)
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{
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dev->reg_shadow[MSM_SPM_REG_SAW_SLP_RST_EN] = slp_rst_en;
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}
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static inline void msm_spm_flush_shadow(
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struct msm_spm_device *dev, unsigned int reg_index)
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{
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__raw_writel(dev->reg_shadow[reg_index],
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dev->reg_base_addr + msm_spm_reg_offsets[reg_index]);
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}
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static inline void msm_spm_load_shadow(
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struct msm_spm_device *dev, unsigned int reg_index)
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{
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dev->reg_shadow[reg_index] = __raw_readl(dev->reg_base_addr +
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msm_spm_reg_offsets[reg_index]);
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}
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static inline uint32_t msm_spm_get_sts_pmic_state(struct msm_spm_device *dev)
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{
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return (dev->reg_shadow[MSM_SPM_REG_SAW_STS] >> 20) & 0x03;
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}
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static inline uint32_t msm_spm_get_sts_curr_pmic_data(
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struct msm_spm_device *dev)
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{
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return (dev->reg_shadow[MSM_SPM_REG_SAW_STS] >> 10) & 0xFF;
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}
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/******************************************************************************
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* Public functions
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*****************************************************************************/
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/**
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* msm_spm_set_low_power_mode() - Configure SPM start address for low power mode
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* @mode: SPM LPM mode to enter
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* @notify_rpm: Notify RPM in this mode
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*/
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int msm_spm_set_low_power_mode(unsigned int mode, bool notify_rpm)
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{
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struct msm_spm_device *dev = &__get_cpu_var(msm_spm_devices);
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uint32_t rpm_bypass = notify_rpm ? 0x00 : 0x01;
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if (mode == dev->low_power_mode && notify_rpm == dev->notify_rpm
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&& !dev->dirty)
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return 0;
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switch (mode) {
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case MSM_SPM_MODE_CLOCK_GATING:
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msm_spm_set_spm_ctl(dev, rpm_bypass, 0x00);
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msm_spm_set_slp_rst_en(dev, 0x00);
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break;
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case MSM_SPM_MODE_POWER_RETENTION:
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msm_spm_set_spm_ctl(dev, rpm_bypass, 0x02);
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msm_spm_set_pmic_ctl(dev, dev->awake_vlevel,
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dev->retention_mid_vlevel, dev->retention_vlevel);
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msm_spm_set_slp_rst_en(dev, 0x00);
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break;
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case MSM_SPM_MODE_POWER_COLLAPSE:
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msm_spm_set_spm_ctl(dev, rpm_bypass, 0x02);
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msm_spm_set_pmic_ctl(dev, dev->awake_vlevel,
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dev->collapse_mid_vlevel, dev->collapse_vlevel);
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msm_spm_set_slp_rst_en(dev, 0x01);
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break;
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default:
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BUG();
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}
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msm_spm_flush_shadow(dev, MSM_SPM_REG_SAW_SPM_CTL);
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msm_spm_flush_shadow(dev, MSM_SPM_REG_SAW_SPM_PMIC_CTL);
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msm_spm_flush_shadow(dev, MSM_SPM_REG_SAW_SLP_RST_EN);
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/* Ensure that the registers are written before returning */
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mb();
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dev->low_power_mode = mode;
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dev->notify_rpm = notify_rpm;
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dev->dirty = false;
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if (msm_spm_debug_mask & MSM_SPM_DEBUG_SHADOW) {
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int i;
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for (i = 0; i < MSM_SPM_REG_NR; i++)
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pr_info("%s: reg %02x = 0x%08x\n", __func__,
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msm_spm_reg_offsets[i], dev->reg_shadow[i]);
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}
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return 0;
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}
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/**
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* msm_spm_set_vdd(): Set core voltage
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* @cpu: core id
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* @vlevel: Encoded PMIC data.
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*/
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int msm_spm_set_vdd(unsigned int cpu, unsigned int vlevel)
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{
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struct msm_spm_device *dev;
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uint32_t timeout_us;
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dev = &per_cpu(msm_spm_devices, cpu);
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if (msm_spm_debug_mask & MSM_SPM_DEBUG_VCTL)
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pr_info("%s: requesting cpu %u vlevel 0x%x\n",
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__func__, cpu, vlevel);
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msm_spm_set_vctl(dev, vlevel);
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msm_spm_flush_shadow(dev, MSM_SPM_REG_SAW_VCTL);
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/* Wait for PMIC state to return to idle or until timeout */
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timeout_us = dev->vctl_timeout_us;
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msm_spm_load_shadow(dev, MSM_SPM_REG_SAW_STS);
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while (msm_spm_get_sts_pmic_state(dev) != MSM_SPM_PMIC_STATE_IDLE) {
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if (!timeout_us)
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goto set_vdd_bail;
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if (timeout_us > 10) {
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udelay(10);
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timeout_us -= 10;
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} else {
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udelay(timeout_us);
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timeout_us = 0;
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}
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msm_spm_load_shadow(dev, MSM_SPM_REG_SAW_STS);
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}
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if (msm_spm_get_sts_curr_pmic_data(dev) != vlevel)
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goto set_vdd_bail;
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dev->awake_vlevel = vlevel;
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dev->dirty = true;
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if (msm_spm_debug_mask & MSM_SPM_DEBUG_VCTL)
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pr_info("%s: cpu %u done, remaining timeout %uus\n",
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__func__, cpu, timeout_us);
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return 0;
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set_vdd_bail:
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pr_err("%s: cpu %u failed, remaining timeout %uus, vlevel 0x%x\n",
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__func__, cpu, timeout_us, msm_spm_get_sts_curr_pmic_data(dev));
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return -EIO;
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}
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/**
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* msm_spm_get_vdd(): Get core voltage
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* @cpu: core id
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* @return: Returns encoded PMIC data.
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*/
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unsigned int msm_spm_get_vdd(unsigned int cpu)
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{
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struct msm_spm_device *dev = &per_cpu(msm_spm_devices, cpu);
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return dev->reg_shadow[MSM_SPM_REG_SAW_VCTL];
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}
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void msm_spm_reinit(void)
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{
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struct msm_spm_device *dev = &__get_cpu_var(msm_spm_devices);
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int i;
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for (i = 0; i < MSM_SPM_REG_NR_INITIALIZE; i++)
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msm_spm_flush_shadow(dev, i);
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/* Ensure that the registers are written before returning */
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mb();
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}
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/**
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* msm_spm_init(): Board initalization function
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* @data: platform specific SPM register configuration data
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* @nr_devs: Number of SPM devices being initialized
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*/
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int __init msm_spm_init(struct msm_spm_platform_data *data, int nr_devs)
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{
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unsigned int cpu;
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BUG_ON(nr_devs < num_possible_cpus());
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for_each_possible_cpu(cpu) {
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struct msm_spm_device *dev = &per_cpu(msm_spm_devices, cpu);
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int i;
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dev->reg_base_addr = data[cpu].reg_base_addr;
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memcpy(dev->reg_shadow, data[cpu].reg_init_values,
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sizeof(data[cpu].reg_init_values));
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dev->awake_vlevel = data[cpu].awake_vlevel;
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dev->retention_vlevel = data[cpu].retention_vlevel;
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dev->collapse_vlevel = data[cpu].collapse_vlevel;
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dev->retention_mid_vlevel = data[cpu].retention_mid_vlevel;
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dev->collapse_mid_vlevel = data[cpu].collapse_mid_vlevel;
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dev->vctl_timeout_us = data[cpu].vctl_timeout_us;
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for (i = 0; i < MSM_SPM_REG_NR_INITIALIZE; i++)
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msm_spm_flush_shadow(dev, i);
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/* Ensure that the registers are written before returning */
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mb();
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dev->low_power_mode = MSM_SPM_MODE_CLOCK_GATING;
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dev->notify_rpm = false;
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dev->dirty = true;
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}
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return 0;
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}
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