550 lines
14 KiB
C
550 lines
14 KiB
C
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/* Copyright (c) 2010-2012, The Linux Foundation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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* only version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*/
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#include <linux/module.h>
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#include <linux/kernel.h>
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#include <linux/types.h>
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#include <linux/bitmap.h>
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#include <linux/bitops.h>
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#include <linux/init.h>
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#include <linux/interrupt.h>
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#include <linux/io.h>
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#include <linux/irq.h>
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#include <linux/slab.h>
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#include <linux/spinlock.h>
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#include <asm/hardware/gic.h>
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#include <mach/msm_iomap.h>
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#include <mach/gpio.h>
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#include <mach/mpm.h>
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/******************************************************************************
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* Debug Definitions
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*****************************************************************************/
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enum {
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MSM_MPM_DEBUG_NON_DETECTABLE_IRQ = BIT(0),
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MSM_MPM_DEBUG_PENDING_IRQ = BIT(1),
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MSM_MPM_DEBUG_WRITE = BIT(2),
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MSM_MPM_DEBUG_NON_DETECTABLE_IRQ_IDLE = BIT(3),
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};
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static int msm_mpm_debug_mask = 1;
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module_param_named(
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debug_mask, msm_mpm_debug_mask, int, S_IRUGO | S_IWUSR | S_IWGRP
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);
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/******************************************************************************
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* Request and Status Definitions
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*****************************************************************************/
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enum {
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MSM_MPM_REQUEST_REG_ENABLE,
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MSM_MPM_REQUEST_REG_DETECT_CTL,
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MSM_MPM_REQUEST_REG_POLARITY,
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MSM_MPM_REQUEST_REG_CLEAR,
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};
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enum {
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MSM_MPM_STATUS_REG_PENDING,
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};
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/******************************************************************************
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* IRQ Mapping Definitions
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*****************************************************************************/
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#define MSM_MPM_NR_APPS_IRQS (NR_MSM_IRQS + NR_GPIO_IRQS)
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#define MSM_MPM_REG_WIDTH DIV_ROUND_UP(MSM_MPM_NR_MPM_IRQS, 32)
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#define MSM_MPM_IRQ_INDEX(irq) (irq / 32)
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#define MSM_MPM_IRQ_MASK(irq) BIT(irq % 32)
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static struct msm_mpm_device_data msm_mpm_dev_data;
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static uint8_t msm_mpm_irqs_a2m[MSM_MPM_NR_APPS_IRQS];
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static DEFINE_SPINLOCK(msm_mpm_lock);
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/*
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* Note: the following two bitmaps only mark irqs that are _not_
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* mappable to MPM.
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*/
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static DECLARE_BITMAP(msm_mpm_enabled_apps_irqs, MSM_MPM_NR_APPS_IRQS);
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static DECLARE_BITMAP(msm_mpm_wake_apps_irqs, MSM_MPM_NR_APPS_IRQS);
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static DECLARE_BITMAP(msm_mpm_gpio_irqs_mask, MSM_MPM_NR_APPS_IRQS);
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static uint32_t msm_mpm_enabled_irq[MSM_MPM_REG_WIDTH];
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static uint32_t msm_mpm_wake_irq[MSM_MPM_REG_WIDTH];
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static uint32_t msm_mpm_detect_ctl[MSM_MPM_REG_WIDTH];
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static uint32_t msm_mpm_polarity[MSM_MPM_REG_WIDTH];
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/******************************************************************************
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* Low Level Functions for Accessing MPM
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*****************************************************************************/
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static inline uint32_t msm_mpm_read(
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unsigned int reg, unsigned int subreg_index)
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{
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unsigned int offset = reg * MSM_MPM_REG_WIDTH + subreg_index;
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return __raw_readl(msm_mpm_dev_data.mpm_status_reg_base + offset * 4);
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}
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static inline void msm_mpm_write(
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unsigned int reg, unsigned int subreg_index, uint32_t value)
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{
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unsigned int offset = reg * MSM_MPM_REG_WIDTH + subreg_index;
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__raw_writel(value, msm_mpm_dev_data.mpm_request_reg_base + offset * 4);
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if (MSM_MPM_DEBUG_WRITE & msm_mpm_debug_mask)
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pr_info("%s: reg %u.%u: 0x%08x\n",
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__func__, reg, subreg_index, value);
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}
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static inline void msm_mpm_send_interrupt(void)
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{
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__raw_writel(msm_mpm_dev_data.mpm_apps_ipc_val,
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msm_mpm_dev_data.mpm_apps_ipc_reg);
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/* Ensure the write is complete before returning. */
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mb();
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}
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static irqreturn_t msm_mpm_irq(int irq, void *dev_id)
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{
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return IRQ_HANDLED;
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}
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/******************************************************************************
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* MPM Access Functions
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*****************************************************************************/
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static void msm_mpm_set(bool wakeset)
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{
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uint32_t *irqs;
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unsigned int reg;
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int i;
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irqs = wakeset ? msm_mpm_wake_irq : msm_mpm_enabled_irq;
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for (i = 0; i < MSM_MPM_REG_WIDTH; i++) {
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reg = MSM_MPM_REQUEST_REG_ENABLE;
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msm_mpm_write(reg, i, irqs[i]);
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reg = MSM_MPM_REQUEST_REG_DETECT_CTL;
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msm_mpm_write(reg, i, msm_mpm_detect_ctl[i]);
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reg = MSM_MPM_REQUEST_REG_POLARITY;
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msm_mpm_write(reg, i, msm_mpm_polarity[i]);
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reg = MSM_MPM_REQUEST_REG_CLEAR;
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msm_mpm_write(reg, i, 0xffffffff);
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}
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/* Ensure that the set operation is complete before sending the
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* interrupt
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*/
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mb();
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msm_mpm_send_interrupt();
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}
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static void msm_mpm_clear(void)
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{
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int i;
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for (i = 0; i < MSM_MPM_REG_WIDTH; i++) {
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msm_mpm_write(MSM_MPM_REQUEST_REG_ENABLE, i, 0);
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msm_mpm_write(MSM_MPM_REQUEST_REG_CLEAR, i, 0xffffffff);
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}
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/* Ensure the clear is complete before sending the interrupt */
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mb();
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msm_mpm_send_interrupt();
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}
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/******************************************************************************
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* Interrupt Mapping Functions
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*****************************************************************************/
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static inline bool msm_mpm_is_valid_apps_irq(unsigned int irq)
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{
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return irq < ARRAY_SIZE(msm_mpm_irqs_a2m);
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}
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static inline uint8_t msm_mpm_get_irq_a2m(unsigned int irq)
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{
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return msm_mpm_irqs_a2m[irq];
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}
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static inline void msm_mpm_set_irq_a2m(unsigned int apps_irq,
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unsigned int mpm_irq)
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{
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msm_mpm_irqs_a2m[apps_irq] = (uint8_t) mpm_irq;
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}
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static inline bool msm_mpm_is_valid_mpm_irq(unsigned int irq)
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{
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return irq < msm_mpm_dev_data.irqs_m2a_size;
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}
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static inline uint16_t msm_mpm_get_irq_m2a(unsigned int irq)
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{
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return msm_mpm_dev_data.irqs_m2a[irq];
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}
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static bool msm_mpm_bypass_apps_irq(unsigned int irq)
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{
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int i;
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for (i = 0; i < msm_mpm_dev_data.bypassed_apps_irqs_size; i++)
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if (irq == msm_mpm_dev_data.bypassed_apps_irqs[i])
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return true;
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return false;
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}
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static int msm_mpm_enable_irq_exclusive(
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unsigned int irq, bool enable, bool wakeset)
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{
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uint32_t mpm_irq;
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if (!msm_mpm_is_valid_apps_irq(irq))
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return -EINVAL;
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if (msm_mpm_bypass_apps_irq(irq))
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return 0;
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mpm_irq = msm_mpm_get_irq_a2m(irq);
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if (mpm_irq) {
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uint32_t *mpm_irq_masks = wakeset ?
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msm_mpm_wake_irq : msm_mpm_enabled_irq;
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uint32_t index = MSM_MPM_IRQ_INDEX(mpm_irq);
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uint32_t mask = MSM_MPM_IRQ_MASK(mpm_irq);
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if (enable)
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mpm_irq_masks[index] |= mask;
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else
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mpm_irq_masks[index] &= ~mask;
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} else {
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unsigned long *apps_irq_bitmap = wakeset ?
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msm_mpm_wake_apps_irqs : msm_mpm_enabled_apps_irqs;
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if (enable)
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__set_bit(irq, apps_irq_bitmap);
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else
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__clear_bit(irq, apps_irq_bitmap);
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}
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return 0;
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}
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static int msm_mpm_set_irq_type_exclusive(
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unsigned int irq, unsigned int flow_type)
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{
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uint32_t mpm_irq;
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if (!msm_mpm_is_valid_apps_irq(irq))
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return -EINVAL;
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if (msm_mpm_bypass_apps_irq(irq))
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return 0;
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mpm_irq = msm_mpm_get_irq_a2m(irq);
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if (mpm_irq) {
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uint32_t index = MSM_MPM_IRQ_INDEX(mpm_irq);
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uint32_t mask = MSM_MPM_IRQ_MASK(mpm_irq);
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if (index >= MSM_MPM_REG_WIDTH)
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return -EFAULT;
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if (flow_type & IRQ_TYPE_EDGE_BOTH)
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msm_mpm_detect_ctl[index] |= mask;
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else
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msm_mpm_detect_ctl[index] &= ~mask;
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if (flow_type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_LEVEL_HIGH))
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msm_mpm_polarity[index] |= mask;
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else
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msm_mpm_polarity[index] &= ~mask;
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}
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return 0;
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}
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static int __msm_mpm_enable_irq(unsigned int irq, unsigned int enable)
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{
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unsigned long flags;
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int rc;
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spin_lock_irqsave(&msm_mpm_lock, flags);
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rc = msm_mpm_enable_irq_exclusive(irq, (bool)enable, false);
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spin_unlock_irqrestore(&msm_mpm_lock, flags);
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return rc;
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}
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static void msm_mpm_enable_irq(struct irq_data *d)
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{
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__msm_mpm_enable_irq(d->irq, 1);
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}
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static void msm_mpm_disable_irq(struct irq_data *d)
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{
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__msm_mpm_enable_irq(d->irq, 0);
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}
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static int msm_mpm_set_irq_wake(struct irq_data *d, unsigned int on)
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{
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unsigned long flags;
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int rc;
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spin_lock_irqsave(&msm_mpm_lock, flags);
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rc = msm_mpm_enable_irq_exclusive(d->irq, (bool)on, true);
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spin_unlock_irqrestore(&msm_mpm_lock, flags);
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return rc;
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}
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static int msm_mpm_set_irq_type(struct irq_data *d, unsigned int flow_type)
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{
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unsigned long flags;
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int rc;
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spin_lock_irqsave(&msm_mpm_lock, flags);
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rc = msm_mpm_set_irq_type_exclusive(d->irq, flow_type);
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spin_unlock_irqrestore(&msm_mpm_lock, flags);
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return rc;
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}
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/******************************************************************************
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* Public functions
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*****************************************************************************/
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int msm_mpm_enable_pin(unsigned int pin, unsigned int enable)
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{
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uint32_t index = MSM_MPM_IRQ_INDEX(pin);
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uint32_t mask = MSM_MPM_IRQ_MASK(pin);
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unsigned long flags;
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spin_lock_irqsave(&msm_mpm_lock, flags);
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if (enable)
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msm_mpm_enabled_irq[index] |= mask;
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else
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msm_mpm_enabled_irq[index] &= ~mask;
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spin_unlock_irqrestore(&msm_mpm_lock, flags);
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return 0;
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}
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int msm_mpm_set_pin_wake(unsigned int pin, unsigned int on)
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{
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uint32_t index = MSM_MPM_IRQ_INDEX(pin);
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uint32_t mask = MSM_MPM_IRQ_MASK(pin);
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unsigned long flags;
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spin_lock_irqsave(&msm_mpm_lock, flags);
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if (on)
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msm_mpm_wake_irq[index] |= mask;
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else
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msm_mpm_wake_irq[index] &= ~mask;
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spin_unlock_irqrestore(&msm_mpm_lock, flags);
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return 0;
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}
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int msm_mpm_set_pin_type(unsigned int pin, unsigned int flow_type)
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{
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uint32_t index = MSM_MPM_IRQ_INDEX(pin);
|
||
|
|
uint32_t mask = MSM_MPM_IRQ_MASK(pin);
|
||
|
|
unsigned long flags;
|
||
|
|
|
||
|
|
spin_lock_irqsave(&msm_mpm_lock, flags);
|
||
|
|
|
||
|
|
if (flow_type & IRQ_TYPE_EDGE_BOTH)
|
||
|
|
msm_mpm_detect_ctl[index] |= mask;
|
||
|
|
else
|
||
|
|
msm_mpm_detect_ctl[index] &= ~mask;
|
||
|
|
|
||
|
|
if (flow_type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_LEVEL_HIGH))
|
||
|
|
msm_mpm_polarity[index] |= mask;
|
||
|
|
else
|
||
|
|
msm_mpm_polarity[index] &= ~mask;
|
||
|
|
|
||
|
|
spin_unlock_irqrestore(&msm_mpm_lock, flags);
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
|
||
|
|
bool msm_mpm_irqs_detectable(bool from_idle)
|
||
|
|
{
|
||
|
|
unsigned long *apps_irq_bitmap;
|
||
|
|
int debug_mask;
|
||
|
|
int i = 0;
|
||
|
|
|
||
|
|
if (from_idle) {
|
||
|
|
apps_irq_bitmap = msm_mpm_enabled_apps_irqs;
|
||
|
|
debug_mask = msm_mpm_debug_mask &
|
||
|
|
MSM_MPM_DEBUG_NON_DETECTABLE_IRQ_IDLE;
|
||
|
|
} else {
|
||
|
|
apps_irq_bitmap = msm_mpm_wake_apps_irqs;
|
||
|
|
debug_mask = msm_mpm_debug_mask &
|
||
|
|
MSM_MPM_DEBUG_NON_DETECTABLE_IRQ;
|
||
|
|
}
|
||
|
|
|
||
|
|
if (debug_mask) {
|
||
|
|
i = find_first_bit(apps_irq_bitmap, MSM_MPM_NR_APPS_IRQS);
|
||
|
|
while (i < MSM_MPM_NR_APPS_IRQS) {
|
||
|
|
struct irq_desc *desc = i ?
|
||
|
|
irq_to_desc(i) : NULL;
|
||
|
|
pr_info("%s: cannot monitor irq=%d %s\n",
|
||
|
|
__func__, i, desc->name);
|
||
|
|
i = find_next_bit(apps_irq_bitmap,
|
||
|
|
MSM_MPM_NR_APPS_IRQS, i + 1);
|
||
|
|
}
|
||
|
|
|
||
|
|
}
|
||
|
|
return (bool)__bitmap_empty(apps_irq_bitmap, MSM_MPM_NR_APPS_IRQS);
|
||
|
|
}
|
||
|
|
|
||
|
|
bool msm_mpm_gpio_irqs_detectable(bool from_idle)
|
||
|
|
{
|
||
|
|
unsigned long *apps_irq_bitmap = from_idle ?
|
||
|
|
msm_mpm_enabled_apps_irqs : msm_mpm_wake_apps_irqs;
|
||
|
|
|
||
|
|
return !__bitmap_intersects(msm_mpm_gpio_irqs_mask, apps_irq_bitmap,
|
||
|
|
MSM_MPM_NR_APPS_IRQS);
|
||
|
|
}
|
||
|
|
|
||
|
|
void msm_mpm_enter_sleep(uint32_t sclk_count, bool from_idle)
|
||
|
|
{
|
||
|
|
msm_mpm_set(!from_idle);
|
||
|
|
}
|
||
|
|
|
||
|
|
void msm_mpm_exit_sleep(bool from_idle)
|
||
|
|
{
|
||
|
|
unsigned long pending;
|
||
|
|
int i;
|
||
|
|
int k;
|
||
|
|
|
||
|
|
for (i = 0; i < MSM_MPM_REG_WIDTH; i++) {
|
||
|
|
pending = msm_mpm_read(MSM_MPM_STATUS_REG_PENDING, i);
|
||
|
|
|
||
|
|
if (MSM_MPM_DEBUG_PENDING_IRQ & msm_mpm_debug_mask)
|
||
|
|
pr_info("%s: pending.%d: 0x%08lx", __func__,
|
||
|
|
i, pending);
|
||
|
|
|
||
|
|
k = find_first_bit(&pending, 32);
|
||
|
|
while (k < 32) {
|
||
|
|
unsigned int mpm_irq = 32 * i + k;
|
||
|
|
unsigned int apps_irq = msm_mpm_get_irq_m2a(mpm_irq);
|
||
|
|
struct irq_desc *desc = apps_irq ?
|
||
|
|
irq_to_desc(apps_irq) : NULL;
|
||
|
|
|
||
|
|
if (desc && !irqd_is_level_type(&desc->irq_data)) {
|
||
|
|
irq_set_pending(apps_irq);
|
||
|
|
if (from_idle)
|
||
|
|
check_irq_resend(desc, apps_irq);
|
||
|
|
}
|
||
|
|
|
||
|
|
k = find_next_bit(&pending, 32, k + 1);
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
msm_mpm_clear();
|
||
|
|
}
|
||
|
|
|
||
|
|
static int __init msm_mpm_early_init(void)
|
||
|
|
{
|
||
|
|
uint8_t mpm_irq;
|
||
|
|
uint16_t apps_irq;
|
||
|
|
|
||
|
|
for (mpm_irq = 0; msm_mpm_is_valid_mpm_irq(mpm_irq); mpm_irq++) {
|
||
|
|
apps_irq = msm_mpm_get_irq_m2a(mpm_irq);
|
||
|
|
if (apps_irq && msm_mpm_is_valid_apps_irq(apps_irq))
|
||
|
|
msm_mpm_set_irq_a2m(apps_irq, mpm_irq);
|
||
|
|
}
|
||
|
|
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
core_initcall(msm_mpm_early_init);
|
||
|
|
|
||
|
|
void __init msm_mpm_irq_extn_init(struct msm_mpm_device_data *mpm_data)
|
||
|
|
{
|
||
|
|
gic_arch_extn.irq_mask = msm_mpm_disable_irq;
|
||
|
|
gic_arch_extn.irq_unmask = msm_mpm_enable_irq;
|
||
|
|
gic_arch_extn.irq_disable = msm_mpm_disable_irq;
|
||
|
|
gic_arch_extn.irq_set_type = msm_mpm_set_irq_type;
|
||
|
|
gic_arch_extn.irq_set_wake = msm_mpm_set_irq_wake;
|
||
|
|
|
||
|
|
msm_gpio_irq_extn.irq_mask = msm_mpm_disable_irq;
|
||
|
|
msm_gpio_irq_extn.irq_unmask = msm_mpm_enable_irq;
|
||
|
|
msm_gpio_irq_extn.irq_disable = msm_mpm_disable_irq;
|
||
|
|
msm_gpio_irq_extn.irq_set_type = msm_mpm_set_irq_type;
|
||
|
|
msm_gpio_irq_extn.irq_set_wake = msm_mpm_set_irq_wake;
|
||
|
|
|
||
|
|
bitmap_set(msm_mpm_gpio_irqs_mask, NR_MSM_IRQS, NR_GPIO_IRQS);
|
||
|
|
|
||
|
|
if (!mpm_data) {
|
||
|
|
#ifdef CONFIG_MSM_MPM
|
||
|
|
BUG();
|
||
|
|
#endif
|
||
|
|
return;
|
||
|
|
}
|
||
|
|
|
||
|
|
memcpy(&msm_mpm_dev_data, mpm_data, sizeof(struct msm_mpm_device_data));
|
||
|
|
|
||
|
|
msm_mpm_dev_data.irqs_m2a =
|
||
|
|
kzalloc(msm_mpm_dev_data.irqs_m2a_size * sizeof(uint16_t),
|
||
|
|
GFP_KERNEL);
|
||
|
|
BUG_ON(!msm_mpm_dev_data.irqs_m2a);
|
||
|
|
memcpy(msm_mpm_dev_data.irqs_m2a, mpm_data->irqs_m2a,
|
||
|
|
msm_mpm_dev_data.irqs_m2a_size * sizeof(uint16_t));
|
||
|
|
msm_mpm_dev_data.bypassed_apps_irqs =
|
||
|
|
kzalloc(msm_mpm_dev_data.bypassed_apps_irqs_size *
|
||
|
|
sizeof(uint16_t), GFP_KERNEL);
|
||
|
|
BUG_ON(!msm_mpm_dev_data.bypassed_apps_irqs);
|
||
|
|
memcpy(msm_mpm_dev_data.bypassed_apps_irqs,
|
||
|
|
mpm_data->bypassed_apps_irqs,
|
||
|
|
msm_mpm_dev_data.bypassed_apps_irqs_size * sizeof(uint16_t));
|
||
|
|
}
|
||
|
|
|
||
|
|
static int __init msm_mpm_init(void)
|
||
|
|
{
|
||
|
|
unsigned int irq = msm_mpm_dev_data.mpm_ipc_irq;
|
||
|
|
int rc;
|
||
|
|
|
||
|
|
rc = request_irq(irq, msm_mpm_irq,
|
||
|
|
IRQF_TRIGGER_RISING, "mpm_drv", msm_mpm_irq);
|
||
|
|
|
||
|
|
if (rc) {
|
||
|
|
pr_err("%s: failed to request irq %u: %d\n",
|
||
|
|
__func__, irq, rc);
|
||
|
|
goto init_bail;
|
||
|
|
}
|
||
|
|
|
||
|
|
rc = irq_set_irq_wake(irq, 1);
|
||
|
|
if (rc) {
|
||
|
|
pr_err("%s: failed to set wakeup irq %u: %d\n",
|
||
|
|
__func__, irq, rc);
|
||
|
|
goto init_free_bail;
|
||
|
|
}
|
||
|
|
|
||
|
|
return 0;
|
||
|
|
|
||
|
|
init_free_bail:
|
||
|
|
free_irq(irq, msm_mpm_irq);
|
||
|
|
|
||
|
|
init_bail:
|
||
|
|
return rc;
|
||
|
|
}
|
||
|
|
device_initcall(msm_mpm_init);
|