408 lines
9.3 KiB
ArmAsm
408 lines
9.3 KiB
ArmAsm
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/*
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* Idle processing for ARMv7-based Qualcomm SoCs.
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*
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* Copyright (C) 2007 Google, Inc.
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* Copyright (c) 2007-2009, 2011-2013 The Linux Foundation. All rights reserved.
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*
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* This software is licensed under the terms of the GNU General Public
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* License version 2, as published by the Free Software Foundation, and
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* may be copied, distributed, and modified under those terms.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*/
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#include <linux/linkage.h>
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#include <linux/threads.h>
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#include <asm/assembler.h>
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#include "idle.h"
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#include "idle-macros.S"
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#ifdef CONFIG_MSM_SCM
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#define SCM_SVC_BOOT 0x1
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#define SCM_CMD_TERMINATE_PC 0x2
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#endif
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ENTRY(msm_arch_idle)
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#ifdef CONFIG_ARCH_MSM_KRAIT
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mrc p15, 0, r0, c0, c0, 0
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bic r1, r0, #0xff
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movw r2, #0x0400
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movt r2, #0x511F
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movw r3, #0x0600
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movt r3, #0x510F
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cmp r2, r1
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cmpne r3, r1
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bne go_wfi
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mrs r0, cpsr
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cpsid if
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mrc p15, 7, r1, c15, c0, 5
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bic r2, r1, #0x20000
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mcr p15, 7, r2, c15, c0, 5
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isb
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go_wfi:
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wfi
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bne wfi_done
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mcr p15, 7, r1, c15, c0, 5
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isb
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msr cpsr_c, r0
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wfi_done:
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bx lr
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#else
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wfi
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#ifdef CONFIG_ARCH_MSM8X60
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mrc p14, 1, r1, c1, c5, 4 /* read ETM PDSR to clear sticky bit */
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mrc p14, 0, r1, c1, c5, 4 /* read DBG PRSR to clear sticky bit */
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isb
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#endif
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bx lr
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#endif
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ENTRY(msm_pm_collapse)
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#if defined(CONFIG_MSM_FIQ_SUPPORT)
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cpsid f
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#endif
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ldr r0, =msm_saved_state /* address of msm_saved_state ptr */
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ldr r0, [r0] /* load ptr */
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#if (NR_CPUS >= 2)
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mrc p15, 0, r1, c0, c0, 5 /* MPIDR */
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ands r1, r1, #15 /* What CPU am I */
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mov r2, #CPU_SAVED_STATE_SIZE
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mul r1, r1, r2
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add r0, r0, r1
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#endif
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stmia r0!, {r4-r14}
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mrc p15, 0, r1, c1, c0, 0 /* MMU control */
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mrc p15, 0, r2, c2, c0, 0 /* TTBR0 */
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mrc p15, 0, r3, c3, c0, 0 /* dacr */
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#ifdef CONFIG_ARCH_MSM_SCORPION
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/* This instruction is not valid for non scorpion processors */
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mrc p15, 3, r4, c15, c0, 3 /* L2CR1 is the L2 cache control reg 1 */
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#endif
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mrc p15, 0, r5, c10, c2, 0 /* PRRR */
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mrc p15, 0, r6, c10, c2, 1 /* NMRR */
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mrc p15, 0, r7, c1, c0, 1 /* ACTLR */
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mrc p15, 0, r8, c2, c0, 1 /* TTBR1 */
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mrc p15, 0, r9, c13, c0, 3 /* TPIDRURO */
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mrc p15, 0, ip, c13, c0, 1 /* context ID */
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stmia r0!, {r1-r9, ip}
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#if defined(CONFIG_MSM_JTAG) || defined(CONFIG_MSM_JTAG_MM)
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bl msm_jtag_save_state
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#endif
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ldr r0, =msm_pm_flush_l2_flag
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ldr r0, [r0]
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mov r1, #0
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mcr p15, 2, r1, c0, c0, 0 /*CCSELR*/
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isb
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mrc p15, 1, r1, c0, c0, 0 /*CCSIDR*/
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mov r2, #1
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and r1, r2, r1, ASR #30 /* Check if the cache is write back */
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orr r1, r0, r1
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cmp r1, #1
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bne skip
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bl v7_flush_dcache_all
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ldr r1, =msm_pm_flush_l2_fn
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ldr r1, [r1]
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cmp r1, #0
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blxne r1
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skip:
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ldr r1, =msm_pm_disable_l2_fn
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ldr r1, [r1]
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cmp r1, #0
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blxne r1
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dmb
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mrc p15, 0, r0, c0, c0, 5 /* MPIDR */
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and r0, r0, #15 /* what CPU am I */
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ldr r1, =msm_pc_debug_counters /*load the IMEM debug location */
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ldr r1, [r1]
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cmp r1, #0
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beq skip_pc_debug1
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add r1, r1, r0, LSL #4 /* debug location for this CPU */
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ldr r2, [r1]
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add r2, #1
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str r2, [r1]
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skip_pc_debug1:
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#ifdef CONFIG_MSM_SCM
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ldr r0, =SCM_SVC_BOOT
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ldr r1, =SCM_CMD_TERMINATE_PC
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ldr r2, =msm_pm_flush_l2_flag
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ldr r2, [r2]
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bl scm_call_atomic1
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#else
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mrc p15, 0, r4, c1, c0, 0 /* read current CR */
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bic r0, r4, #(1 << 2) /* clear dcache bit */
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bic r0, r0, #(1 << 12) /* clear icache bit */
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mcr p15, 0, r0, c1, c0, 0 /* disable d/i cache */
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isb
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SUSPEND_8x25_L2
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SET_SMP_COHERENCY OFF
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wfi
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DELAY_8x25 300
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mcr p15, 0, r4, c1, c0, 0 /* restore d/i cache */
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isb
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ENABLE_8x25_L2 /* enable only l2, no need to restore the reg back */
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SET_SMP_COHERENCY ON
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#endif
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#if defined(CONFIG_MSM_FIQ_SUPPORT)
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cpsie f
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#endif
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mrc p15, 0, r0, c0, c0, 5 /* MPIDR */
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and r0, r0, #15 /* what CPU am I */
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ldr r1, =msm_pc_debug_counters /*load the IMEM debug location */
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ldr r1, [r1]
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cmp r1, #0
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beq skip_pc_debug2
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add r1, r1, r0, LSL #4 /* debug location for this CPU */
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add r1, #8
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ldr r2, [r1]
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add r2, #1
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str r2, [r1]
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skip_pc_debug2:
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ldr r1, =msm_pm_enable_l2_fn
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ldr r1, [r1]
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cmp r1, #0
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blxne r1
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dmb
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#if defined(CONFIG_MSM_JTAG) || defined(CONFIG_MSM_JTAG_MM)
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bl msm_jtag_restore_state
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#endif
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ldr r0, =msm_saved_state /* address of msm_saved_state ptr */
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ldr r0, [r0] /* load ptr */
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#if (NR_CPUS >= 2)
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mrc p15, 0, r1, c0, c0, 5 /* MPIDR */
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ands r1, r1, #15 /* What CPU am I */
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mov r2, #CPU_SAVED_STATE_SIZE
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mul r2, r2, r1
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add r0, r0, r2
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#endif
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ldmfd r0, {r4-r14} /* restore registers */
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mov r0, #0 /* return power collapse failed */
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bx lr
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ENTRY(msm_pm_collapse_exit)
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#if 0 /* serial debug */
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mov r0, #0x80000016
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mcr p15, 0, r0, c15, c2, 4
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mov r0, #0xA9000000
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add r0, r0, #0x00A00000 /* UART1 */
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/*add r0, r0, #0x00C00000*/ /* UART3 */
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mov r1, #'A'
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str r1, [r0, #0x00C]
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#endif
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ldr r1, =msm_saved_state_phys
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ldr r2, =msm_pm_collapse_exit
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adr r3, msm_pm_collapse_exit
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add r1, r1, r3
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sub r1, r1, r2
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ldr r1, [r1]
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add r1, r1, #CPU_SAVED_STATE_SIZE
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#if (NR_CPUS >= 2)
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mrc p15, 0, r2, c0, c0, 5 /* MPIDR */
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ands r2, r2, #15 /* What CPU am I */
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mov r3, #CPU_SAVED_STATE_SIZE
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mul r2, r2, r3
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add r1, r1, r2
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#endif
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ldmdb r1!, {r2-r11}
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mcr p15, 0, r4, c3, c0, 0 /* dacr */
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mcr p15, 0, r3, c2, c0, 0 /* TTBR0 */
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#ifdef CONFIG_ARCH_MSM_SCORPION
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/* This instruction is not valid for non scorpion processors */
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mcr p15, 3, r5, c15, c0, 3 /* L2CR1 */
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#endif
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mcr p15, 0, r6, c10, c2, 0 /* PRRR */
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mcr p15, 0, r7, c10, c2, 1 /* NMRR */
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mcr p15, 0, r8, c1, c0, 1 /* ACTLR */
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mcr p15, 0, r9, c2, c0, 1 /* TTBR1 */
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mcr p15, 0, r10, c13, c0, 3 /* TPIDRURO */
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mcr p15, 0, r11, c13, c0, 1 /* context ID */
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isb
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ldmdb r1!, {r4-r14}
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ldr r0, =msm_pm_pc_pgd
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ldr r1, =msm_pm_collapse_exit
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adr r3, msm_pm_collapse_exit
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add r0, r0, r3
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sub r0, r0, r1
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ldr r0, [r0]
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mrc p15, 0, r1, c2, c0, 0 /* save current TTBR0 */
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and r3, r1, #0x7f /* mask to get TTB flags */
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orr r0, r0, r3 /* add TTB flags to switch TTBR value */
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mcr p15, 0, r0, c2, c0, 0 /* temporary switch TTBR0 */
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isb
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mcr p15, 0, r2, c1, c0, 0 /* MMU control */
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isb
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msm_pm_mapped_pa:
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/* Switch to virtual */
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ldr r0, =msm_pm_pa_to_va
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mov pc, r0
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msm_pm_pa_to_va:
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mcr p15, 0, r1, c2, c0, 0 /* restore TTBR0 */
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isb
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mcr p15, 0, r3, c8, c7, 0 /* UTLBIALL */
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mcr p15, 0, r3, c7, c5, 6 /* BPIALL */
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dsb
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isb
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#ifdef CONFIG_ARCH_MSM_KRAIT
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mrc p15, 0, r1, c0, c0, 0
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ldr r3, =0xff00fc00
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and r3, r1, r3
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ldr r1, =0x51000400
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cmp r3, r1
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mrceq p15, 7, r3, c15, c0, 2
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biceq r3, r3, #0x400
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mcreq p15, 7, r3, c15, c0, 2
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#else
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RESUME_8x25_L2
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SET_SMP_COHERENCY ON
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#endif
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ldr r1, =msm_pm_enable_l2_fn
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ldr r1, [r1]
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cmp r1, #0
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stmfd sp!, {lr}
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blxne r1
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dmb
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#if defined(CONFIG_MSM_JTAG) || defined(CONFIG_MSM_JTAG_MM)
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bl msm_jtag_restore_state
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#endif
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ldmfd sp!, {lr}
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mov r0, #1
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bx lr
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nop
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nop
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nop
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nop
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nop
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1: b 1b
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ENTRY(msm_pm_boot_entry)
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mrc p15, 0, r0, c0, c0, 5 /* MPIDR */
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and r0, r0, #15 /* what CPU am I */
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ldr r1, =msm_pc_debug_counters_phys /*phys addr for IMEM reg */
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ldr r2, =msm_pm_boot_entry
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adr r3, msm_pm_boot_entry
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add r1, r1, r3 /* translate virt to phys addr */
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sub r1, r1, r2
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ldr r1,[r1]
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cmp r1, #0
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beq skip_pc_debug3
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add r1, r1, r0, LSL #4 /* debug location for this CPU */
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add r1, #4 /* warmboot entry counter*/
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ldr r2, [r1]
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add r2, #1
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str r2, [r1]
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skip_pc_debug3:
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ldr r1, =msm_pm_boot_vector
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ldr r2, =msm_pm_boot_entry
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adr r3, msm_pm_boot_entry
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add r1, r1, r3 /* translate virt to phys addr */
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sub r1, r1, r2
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add r1, r1, r0, LSL #2 /* locate boot vector for our cpu */
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ldr pc, [r1] /* jump */
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ENTRY(msm_pm_set_l2_flush_flag)
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ldr r1, =msm_pm_flush_l2_flag
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str r0, [r1]
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bx lr
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ENTRY(msm_pm_get_l2_flush_flag)
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ldr r1, =msm_pm_flush_l2_flag
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ldr r0, [r1]
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bx lr
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.data
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|
|
||
|
|
.globl msm_pm_pc_pgd
|
||
|
|
msm_pm_pc_pgd:
|
||
|
|
.long 0x0
|
||
|
|
|
||
|
|
.globl msm_saved_state
|
||
|
|
msm_saved_state:
|
||
|
|
.long 0x0
|
||
|
|
|
||
|
|
.globl msm_saved_state_phys
|
||
|
|
msm_saved_state_phys:
|
||
|
|
.long 0x0
|
||
|
|
|
||
|
|
.globl msm_pm_boot_vector
|
||
|
|
msm_pm_boot_vector:
|
||
|
|
.space 4 * NR_CPUS
|
||
|
|
|
||
|
|
.globl target_type
|
||
|
|
target_type:
|
||
|
|
.long 0x0
|
||
|
|
|
||
|
|
.globl apps_power_collapse
|
||
|
|
apps_power_collapse:
|
||
|
|
.long 0x0
|
||
|
|
|
||
|
|
.globl l2x0_base_addr
|
||
|
|
l2x0_base_addr:
|
||
|
|
.long 0x0
|
||
|
|
|
||
|
|
.globl msm_pc_debug_counters_phys
|
||
|
|
msm_pc_debug_counters_phys:
|
||
|
|
.long 0x0
|
||
|
|
|
||
|
|
.globl msm_pc_debug_counters
|
||
|
|
msm_pc_debug_counters:
|
||
|
|
.long 0x0
|
||
|
|
|
||
|
|
.globl msm_pm_enable_l2_fn
|
||
|
|
msm_pm_enable_l2_fn:
|
||
|
|
.long 0x0
|
||
|
|
|
||
|
|
.globl msm_pm_disable_l2_fn
|
||
|
|
msm_pm_disable_l2_fn:
|
||
|
|
.long 0x0
|
||
|
|
|
||
|
|
.globl msm_pm_flush_l2_fn
|
||
|
|
msm_pm_flush_l2_fn:
|
||
|
|
.long 0x0
|
||
|
|
|
||
|
|
/*
|
||
|
|
* Default the l2 flush flag to 1 so that caches are flushed during power
|
||
|
|
* collapse unless the L2 driver decides to flush them only during L2
|
||
|
|
* Power collapse.
|
||
|
|
*/
|
||
|
|
msm_pm_flush_l2_flag:
|
||
|
|
.long 0x1
|
||
|
|
|
||
|
|
/*
|
||
|
|
* Save & restore l2x0 registers while system is entering and resuming
|
||
|
|
* from Power Collapse.
|
||
|
|
* 1. aux_ctrl_save (0x0)
|
||
|
|
* 2. data_latency_ctrl (0x4)
|
||
|
|
* 3. prefetch control (0x8)
|
||
|
|
*/
|
||
|
|
l2x0_saved_ctrl_reg_val:
|
||
|
|
.space 4 * 3
|