291 lines
7.6 KiB
C
291 lines
7.6 KiB
C
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/* Copyright (c) 2009-2012, The Linux Foundation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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* only version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*/
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#ifndef __ARCH_ARM_MACH_MSM_CLOCK_LOCAL_H
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#define __ARCH_ARM_MACH_MSM_CLOCK_LOCAL_H
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#include <linux/spinlock.h>
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#include <mach/clk-provider.h>
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#define MN_MODE_DUAL_EDGE 0x2
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/* MD Registers */
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#define MD4(m_lsb, m, n_lsb, n) \
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((BVAL((m_lsb+3), m_lsb, m) | BVAL((n_lsb+3), n_lsb, ~(n))) \
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* !!(n))
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#define MD8(m_lsb, m, n_lsb, n) \
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((BVAL((m_lsb+7), m_lsb, m) | BVAL((n_lsb+7), n_lsb, ~(n))) \
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* !!(n))
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#define MD16(m, n) ((BVAL(31, 16, m) | BVAL(15, 0, ~(n))) * !!(n))
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/* NS Registers */
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#define NS(n_msb, n_lsb, n, m, mde_lsb, d_msb, d_lsb, d, s_msb, s_lsb, s) \
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(BVAL(n_msb, n_lsb, ~(n-m) * !!(n)) \
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| (BVAL((mde_lsb+1), mde_lsb, MN_MODE_DUAL_EDGE) * !!(n)) \
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| BVAL(d_msb, d_lsb, (d-1)) | BVAL(s_msb, s_lsb, s))
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#define NS_MM(n_msb, n_lsb, n, m, d_msb, d_lsb, d, s_msb, s_lsb, s) \
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(BVAL(n_msb, n_lsb, ~(n-m) * !!(n))|BVAL(d_msb, d_lsb, (d-1)) \
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| BVAL(s_msb, s_lsb, s))
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#define NS_DIVSRC(d_msb, d_lsb, d, s_msb, s_lsb, s) \
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(BVAL(d_msb, d_lsb, (d-1)) | BVAL(s_msb, s_lsb, s))
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#define NS_DIV(d_msb, d_lsb, d) \
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BVAL(d_msb, d_lsb, (d-1))
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#define NS_SRC_SEL(s_msb, s_lsb, s) \
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BVAL(s_msb, s_lsb, s)
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#define NS_MND_BANKED4(n0_lsb, n1_lsb, n, m, s0_lsb, s1_lsb, s) \
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(BVAL((n0_lsb+3), n0_lsb, ~(n-m) * !!(n)) \
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| BVAL((n1_lsb+3), n1_lsb, ~(n-m) * !!(n)) \
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| BVAL((s0_lsb+2), s0_lsb, s) \
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| BVAL((s1_lsb+2), s1_lsb, s))
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#define NS_MND_BANKED8(n0_lsb, n1_lsb, n, m, s0_lsb, s1_lsb, s) \
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(BVAL((n0_lsb+7), n0_lsb, ~(n-m) * !!(n)) \
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| BVAL((n1_lsb+7), n1_lsb, ~(n-m) * !!(n)) \
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| BVAL((s0_lsb+2), s0_lsb, s) \
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| BVAL((s1_lsb+2), s1_lsb, s))
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#define NS_DIVSRC_BANKED(d0_msb, d0_lsb, d1_msb, d1_lsb, d, \
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s0_msb, s0_lsb, s1_msb, s1_lsb, s) \
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(BVAL(d0_msb, d0_lsb, (d-1)) | BVAL(d1_msb, d1_lsb, (d-1)) \
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| BVAL(s0_msb, s0_lsb, s) \
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| BVAL(s1_msb, s1_lsb, s))
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/* CC Registers */
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#define CC(mde_lsb, n) (BVAL((mde_lsb+1), mde_lsb, MN_MODE_DUAL_EDGE) * !!(n))
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#define CC_BANKED(mde0_lsb, mde1_lsb, n) \
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((BVAL((mde0_lsb+1), mde0_lsb, MN_MODE_DUAL_EDGE) \
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| BVAL((mde1_lsb+1), mde1_lsb, MN_MODE_DUAL_EDGE)) \
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* !!(n))
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/*
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* Clock Definition Macros
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*/
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#define DEFINE_CLK_MEASURE(name) \
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struct clk name = { \
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.ops = &clk_ops_empty, \
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.dbg_name = #name, \
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CLK_INIT(name), \
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}; \
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/*
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* Generic frequency-definition structs and macros
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*/
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struct clk_freq_tbl {
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const uint32_t freq_hz;
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struct clk *const src_clk;
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const uint32_t md_val;
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const uint32_t ns_val;
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const uint32_t ctl_val;
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void *const extra_freq_data;
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};
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/* Some clocks have two banks to avoid glitches when switching frequencies.
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* The unused bank is programmed while running on the other bank, and
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* switched to afterwards. The following two structs describe the banks. */
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struct bank_mask_info {
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void *const md_reg;
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const uint32_t ns_mask;
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const uint32_t rst_mask;
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const uint32_t mnd_en_mask;
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const uint32_t mode_mask;
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};
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struct bank_masks {
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const uint32_t bank_sel_mask;
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const struct bank_mask_info bank0_mask;
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const struct bank_mask_info bank1_mask;
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};
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#define F_RAW(f, sc, m_v, n_v, c_v, e) { \
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.freq_hz = f, \
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.src_clk = sc, \
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.md_val = m_v, \
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.ns_val = n_v, \
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.ctl_val = c_v, \
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.extra_freq_data = e, \
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}
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#define FREQ_END (UINT_MAX-1)
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#define F_END { .freq_hz = FREQ_END }
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/**
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* struct branch - branch on/off
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* @ctl_reg: clock control register
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* @en_mask: ORed with @ctl_reg to enable the clock
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* @hwcg_reg: hardware clock gating register
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* @hwcg_mask: ORed with @hwcg_reg to enable hardware clock gating
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* @halt_reg: halt register
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* @halt_check: type of halt check to perform
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* @halt_bit: ANDed with @halt_reg to test for clock halted
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* @reset_reg: reset register
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* @reset_mask: ORed with @reset_reg to reset the clock domain
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*/
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struct branch {
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void __iomem *const ctl_reg;
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const u32 en_mask;
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void __iomem *hwcg_reg;
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u32 hwcg_mask;
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void __iomem *const halt_reg;
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const u16 halt_check;
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const u16 halt_bit;
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void __iomem *const reset_reg;
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const u32 reset_mask;
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void __iomem *const retain_reg;
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const u32 retain_mask;
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};
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extern struct clk_ops clk_ops_branch;
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extern struct clk_ops clk_ops_smi_2x;
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extern struct clk_ops clk_ops_reset;
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int branch_reset(struct branch *b, enum clk_reset_action action);
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void __branch_enable_reg(const struct branch *b, const char *name);
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u32 __branch_disable_reg(const struct branch *b, const char *name);
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enum handoff branch_handoff(struct branch *b, struct clk *c);
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/*
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* Generic clock-definition struct and macros
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*/
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struct rcg_clk {
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bool prepared;
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bool enabled;
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void *const ns_reg;
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void *const md_reg;
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const uint32_t root_en_mask;
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uint32_t ns_mask;
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const uint32_t ctl_mask;
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uint32_t mnd_en_mask;
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void *bank_info;
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void (*set_rate)(struct rcg_clk *, struct clk_freq_tbl *);
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struct clk_freq_tbl *freq_tbl;
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struct clk_freq_tbl *current_freq;
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struct branch b;
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struct clk c;
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};
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static inline struct rcg_clk *to_rcg_clk(struct clk *c)
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{
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return container_of(c, struct rcg_clk, c);
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}
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extern struct clk_ops clk_ops_rcg;
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extern struct clk_freq_tbl rcg_dummy_freq;
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/**
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* struct cdiv_clk - integer divider clock with external source selection
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* @ns_reg: source select and divider settings register
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* @ext_mask: bit to set to select an external source
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* @cur_div: current divider setting (or 0 for external source)
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* @max_div: maximum divider value supported (must be power of 2)
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* @div_offset: number of bits to shift divider left by in @ns_reg
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* @b: branch
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* @c: clock
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*/
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struct cdiv_clk {
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void __iomem *const ns_reg;
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u32 ext_mask;
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unsigned long cur_div;
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u8 div_offset;
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u32 max_div;
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struct branch b;
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struct clk c;
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};
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static inline struct cdiv_clk *to_cdiv_clk(struct clk *c)
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{
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return container_of(c, struct cdiv_clk, c);
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}
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extern struct clk_ops clk_ops_cdiv;
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/**
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* struct fixed_clk - fixed rate clock (used for crystal oscillators)
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* @c: clk
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*/
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struct fixed_clk {
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struct clk c;
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};
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/**
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* struct branch_clk - branch
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* @enabled: true if clock is on, false otherwise
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* @b: branch
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* @c: clock
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*
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* An on/off switch with a rate derived from the parent.
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*/
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struct branch_clk {
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bool enabled;
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struct branch b;
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struct clk c;
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};
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static inline struct branch_clk *to_branch_clk(struct clk *c)
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{
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return container_of(c, struct branch_clk, c);
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}
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/**
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* struct measure_clk - for rate measurement debug use
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* @sample_ticks: sample period in reference clock ticks
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* @multiplier: measurement scale-up factor
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* @divider: measurement scale-down factor
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* @c: clock
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*/
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struct measure_clk {
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u64 sample_ticks;
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u32 multiplier;
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u32 divider;
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struct clk c;
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};
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extern struct clk_ops clk_ops_empty;
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static inline struct measure_clk *to_measure_clk(struct clk *c)
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{
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return container_of(c, struct measure_clk, c);
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}
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/*
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* Variables from clock-local driver
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*/
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extern spinlock_t local_clock_reg_lock;
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extern struct fixed_clk gnd_clk;
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/*
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* Generic set-rate implementations
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*/
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void set_rate_mnd(struct rcg_clk *rcg, struct clk_freq_tbl *nf);
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void set_rate_nop(struct rcg_clk *rcg, struct clk_freq_tbl *nf);
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void set_rate_mnd_8(struct rcg_clk *rcg, struct clk_freq_tbl *nf);
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void set_rate_mnd_banked(struct rcg_clk *rcg, struct clk_freq_tbl *nf);
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void set_rate_div_banked(struct rcg_clk *rcg, struct clk_freq_tbl *nf);
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#endif /* __ARCH_ARM_MACH_MSM_CLOCK_LOCAL_H */
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