88 lines
3.2 KiB
C
88 lines
3.2 KiB
C
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/*
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* Header file for the Atmel AHB DMA Controller driver
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*
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* Copyright (C) 2008 Atmel Corporation
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*/
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#ifndef AT_HDMAC_H
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#define AT_HDMAC_H
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#include <linux/dmaengine.h>
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/**
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* struct at_dma_platform_data - Controller configuration parameters
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* @nr_channels: Number of channels supported by hardware (max 8)
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* @cap_mask: dma_capability flags supported by the platform
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*/
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struct at_dma_platform_data {
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unsigned int nr_channels;
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dma_cap_mask_t cap_mask;
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};
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/**
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* struct at_dma_slave - Controller-specific information about a slave
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* @dma_dev: required DMA master device
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* @tx_reg: physical address of data register used for
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* memory-to-peripheral transfers
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* @rx_reg: physical address of data register used for
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* peripheral-to-memory transfers
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* @reg_width: peripheral register width
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* @cfg: Platform-specific initializer for the CFG register
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* @ctrla: Platform-specific initializer for the CTRLA register
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*/
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struct at_dma_slave {
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struct device *dma_dev;
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u32 cfg;
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u32 ctrla;
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};
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/* Platform-configurable bits in CFG */
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#define ATC_SRC_PER(h) (0xFU & (h)) /* Channel src rq associated with periph handshaking ifc h */
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#define ATC_DST_PER(h) ((0xFU & (h)) << 4) /* Channel dst rq associated with periph handshaking ifc h */
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#define ATC_SRC_REP (0x1 << 8) /* Source Replay Mod */
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#define ATC_SRC_H2SEL (0x1 << 9) /* Source Handshaking Mod */
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#define ATC_SRC_H2SEL_SW (0x0 << 9)
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#define ATC_SRC_H2SEL_HW (0x1 << 9)
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#define ATC_DST_REP (0x1 << 12) /* Destination Replay Mod */
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#define ATC_DST_H2SEL (0x1 << 13) /* Destination Handshaking Mod */
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#define ATC_DST_H2SEL_SW (0x0 << 13)
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#define ATC_DST_H2SEL_HW (0x1 << 13)
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#define ATC_SOD (0x1 << 16) /* Stop On Done */
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#define ATC_LOCK_IF (0x1 << 20) /* Interface Lock */
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#define ATC_LOCK_B (0x1 << 21) /* AHB Bus Lock */
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#define ATC_LOCK_IF_L (0x1 << 22) /* Master Interface Arbiter Lock */
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#define ATC_LOCK_IF_L_CHUNK (0x0 << 22)
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#define ATC_LOCK_IF_L_BUFFER (0x1 << 22)
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#define ATC_AHB_PROT_MASK (0x7 << 24) /* AHB Protection */
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#define ATC_FIFOCFG_MASK (0x3 << 28) /* FIFO Request Configuration */
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#define ATC_FIFOCFG_LARGESTBURST (0x0 << 28)
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#define ATC_FIFOCFG_HALFFIFO (0x1 << 28)
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#define ATC_FIFOCFG_ENOUGHSPACE (0x2 << 28)
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/* Platform-configurable bits in CTRLA */
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#define ATC_SCSIZE_MASK (0x7 << 16) /* Source Chunk Transfer Size */
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#define ATC_SCSIZE_1 (0x0 << 16)
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#define ATC_SCSIZE_4 (0x1 << 16)
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#define ATC_SCSIZE_8 (0x2 << 16)
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#define ATC_SCSIZE_16 (0x3 << 16)
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#define ATC_SCSIZE_32 (0x4 << 16)
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#define ATC_SCSIZE_64 (0x5 << 16)
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#define ATC_SCSIZE_128 (0x6 << 16)
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#define ATC_SCSIZE_256 (0x7 << 16)
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#define ATC_DCSIZE_MASK (0x7 << 20) /* Destination Chunk Transfer Size */
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#define ATC_DCSIZE_1 (0x0 << 20)
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#define ATC_DCSIZE_4 (0x1 << 20)
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#define ATC_DCSIZE_8 (0x2 << 20)
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#define ATC_DCSIZE_16 (0x3 << 20)
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#define ATC_DCSIZE_32 (0x4 << 20)
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#define ATC_DCSIZE_64 (0x5 << 20)
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#define ATC_DCSIZE_128 (0x6 << 20)
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#define ATC_DCSIZE_256 (0x7 << 20)
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#endif /* AT_HDMAC_H */
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