23 lines
544 B
Plaintext
23 lines
544 B
Plaintext
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* ARM Performance Monitor Units
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ARM cores often have a PMU for counting cpu and cache events like cache misses
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and hits. The interface to the PMU is part of the ARM ARM. The ARM PMU
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representation in the device tree should be done as under:-
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Required properties:
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- compatible : should be one of
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"arm,cortex-a9-pmu"
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"arm,cortex-a8-pmu"
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"arm,cortex-a7-pmu"
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"arm,arm1176-pmu"
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"arm,arm1136-pmu"
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- interrupts : 1 combined interrupt or 1 per core.
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Example:
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pmu {
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compatible = "arm,cortex-a9-pmu";
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interrupts = <100 101>;
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};
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