60 lines
2.0 KiB
Plaintext
60 lines
2.0 KiB
Plaintext
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* ARM Generic Interrupt Controller
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ARM SMP cores are often associated with a GIC, providing per processor
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interrupts (PPI), shared processor interrupts (SPI) and software
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generated interrupts (SGI).
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Primary GIC is attached directly to the CPU and typically has PPIs and SGIs.
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Secondary GICs are cascaded into the upward interrupt controller and do not
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have PPIs or SGIs.
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Main node required properties:
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- compatible : should be one of:
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"arm,cortex-a9-gic"
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"arm,arm11mp-gic"
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- interrupt-controller : Identifies the node as an interrupt controller
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- #interrupt-cells : Specifies the number of cells needed to encode an
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interrupt source. The type shall be a <u32> and the value shall be 3.
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The 1st cell is the interrupt type; 0 for SPI interrupts, 1 for PPI
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interrupts.
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The 2nd cell contains the interrupt number for the interrupt type.
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SPI interrupts are in the range [0-987]. PPI interrupts are in the
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range [0-15].
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The 3rd cell is the flags, encoded as follows:
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bits[3:0] trigger type and level flags.
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1 = low-to-high edge triggered
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2 = high-to-low edge triggered
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4 = active high level-sensitive
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8 = active low level-sensitive
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bits[15:8] PPI interrupt cpu mask. Each bit corresponds to each of
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the 8 possible cpus attached to the GIC. A bit set to '1' indicated
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the interrupt is wired to that CPU. Only valid for PPI interrupts.
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- reg : Specifies base physical address(s) and size of the GIC registers. The
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first region is the GIC distributor register base and size. The 2nd region is
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the GIC cpu interface register base and size.
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Optional
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- interrupts : Interrupt source of the parent interrupt controller. Only
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present on secondary GICs.
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- cpu-offset : per-cpu offset within the distributor and cpu interface
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regions, used when the GIC doesn't have banked registers. The offset is
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cpu-offset * cpu-nr.
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Example:
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intc: interrupt-controller@fff11000 {
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compatible = "arm,cortex-a9-gic";
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#interrupt-cells = <3>;
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#address-cells = <1>;
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interrupt-controller;
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reg = <0xfff11000 0x1000>,
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<0xfff10100 0x100>;
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};
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