272 lines
8.7 KiB
C
272 lines
8.7 KiB
C
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/******************************************************************************
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*
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* Copyright(c) 2009-2012 Realtek Corporation.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of version 2 of the GNU General Public License as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program; if not, write to the Free Software Foundation, Inc.,
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* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
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*
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* The full GNU General Public License is included in this distribution in the
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* file called LICENSE.
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*
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* Contact Information:
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* wlanfae <wlanfae@realtek.com>
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* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
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* Hsinchu 300, Taiwan.
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*
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* Larry Finger <Larry.Finger@lwfinger.net>
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*
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*****************************************************************************/
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#ifndef __RTL92D_DEF_H__
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#define __RTL92D_DEF_H__
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/* Min Spacing related settings. */
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#define MAX_MSS_DENSITY_2T 0x13
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#define MAX_MSS_DENSITY_1T 0x0A
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#define RF6052_MAX_TX_PWR 0x3F
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#define RF6052_MAX_REG 0x3F
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#define RF6052_MAX_PATH 2
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#define HAL_RETRY_LIMIT_INFRA 48
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#define HAL_RETRY_LIMIT_AP_ADHOC 7
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#define PHY_RSSI_SLID_WIN_MAX 100
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#define PHY_LINKQUALITY_SLID_WIN_MAX 20
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#define PHY_BEACON_RSSI_SLID_WIN_MAX 10
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#define RESET_DELAY_8185 20
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#define RT_IBSS_INT_MASKS (IMR_BCNINT | IMR_TBDOK | IMR_TBDER)
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#define RT_AC_INT_MASKS (IMR_VIDOK | IMR_VODOK | IMR_BEDOK|IMR_BKDOK)
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#define NUM_OF_FIRMWARE_QUEUE 10
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#define NUM_OF_PAGES_IN_FW 0x100
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#define NUM_OF_PAGE_IN_FW_QUEUE_BK 0x07
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#define NUM_OF_PAGE_IN_FW_QUEUE_BE 0x07
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#define NUM_OF_PAGE_IN_FW_QUEUE_VI 0x07
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#define NUM_OF_PAGE_IN_FW_QUEUE_VO 0x07
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#define NUM_OF_PAGE_IN_FW_QUEUE_HCCA 0x0
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#define NUM_OF_PAGE_IN_FW_QUEUE_CMD 0x0
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#define NUM_OF_PAGE_IN_FW_QUEUE_MGNT 0x02
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#define NUM_OF_PAGE_IN_FW_QUEUE_HIGH 0x02
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#define NUM_OF_PAGE_IN_FW_QUEUE_BCN 0x2
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#define NUM_OF_PAGE_IN_FW_QUEUE_PUB 0xA1
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#define NUM_OF_PAGE_IN_FW_QUEUE_BK_DTM 0x026
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#define NUM_OF_PAGE_IN_FW_QUEUE_BE_DTM 0x048
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#define NUM_OF_PAGE_IN_FW_QUEUE_VI_DTM 0x048
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#define NUM_OF_PAGE_IN_FW_QUEUE_VO_DTM 0x026
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#define NUM_OF_PAGE_IN_FW_QUEUE_PUB_DTM 0x00
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#define MAX_LINES_HWCONFIG_TXT 1000
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#define MAX_BYTES_LINE_HWCONFIG_TXT 256
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#define SW_THREE_WIRE 0
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#define HW_THREE_WIRE 2
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#define BT_DEMO_BOARD 0
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#define BT_QA_BOARD 1
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#define BT_FPGA 2
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#define RX_SMOOTH_FACTOR 20
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#define HAL_PRIME_CHNL_OFFSET_DONT_CARE 0
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#define HAL_PRIME_CHNL_OFFSET_LOWER 1
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#define HAL_PRIME_CHNL_OFFSET_UPPER 2
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#define MAX_H2C_QUEUE_NUM 10
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#define RX_MPDU_QUEUE 0
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#define RX_CMD_QUEUE 1
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#define RX_MAX_QUEUE 2
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#define C2H_RX_CMD_HDR_LEN 8
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#define GET_C2H_CMD_CMD_LEN(__prxhdr) \
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LE_BITS_TO_4BYTE((__prxhdr), 0, 16)
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#define GET_C2H_CMD_ELEMENT_ID(__prxhdr) \
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LE_BITS_TO_4BYTE((__prxhdr), 16, 8)
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#define GET_C2H_CMD_CMD_SEQ(__prxhdr) \
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LE_BITS_TO_4BYTE((__prxhdr), 24, 7)
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#define GET_C2H_CMD_CONTINUE(__prxhdr) \
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LE_BITS_TO_4BYTE((__prxhdr), 31, 1)
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#define GET_C2H_CMD_CONTENT(__prxhdr) \
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((u8 *)(__prxhdr) + C2H_RX_CMD_HDR_LEN)
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#define GET_C2H_CMD_FEEDBACK_ELEMENT_ID(__pcmdfbhdr) \
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LE_BITS_TO_4BYTE((__pcmdfbhdr), 0, 8)
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#define GET_C2H_CMD_FEEDBACK_CCX_LEN(__pcmdfbhdr) \
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LE_BITS_TO_4BYTE((__pcmdfbhdr), 8, 8)
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#define GET_C2H_CMD_FEEDBACK_CCX_CMD_CNT(__pcmdfbhdr) \
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LE_BITS_TO_4BYTE((__pcmdfbhdr), 16, 16)
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#define GET_C2H_CMD_FEEDBACK_CCX_MAC_ID(__pcmdfbhdr) \
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LE_BITS_TO_4BYTE(((__pcmdfbhdr) + 4), 0, 5)
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#define GET_C2H_CMD_FEEDBACK_CCX_VALID(__pcmdfbhdr) \
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LE_BITS_TO_4BYTE(((__pcmdfbhdr) + 4), 7, 1)
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#define GET_C2H_CMD_FEEDBACK_CCX_RETRY_CNT(__pcmdfbhdr) \
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LE_BITS_TO_4BYTE(((__pcmdfbhdr) + 4), 8, 5)
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#define GET_C2H_CMD_FEEDBACK_CCX_TOK(__pcmdfbhdr) \
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LE_BITS_TO_4BYTE(((__pcmdfbhdr) + 4), 15, 1)
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#define GET_C2H_CMD_FEEDBACK_CCX_QSEL(__pcmdfbhdr) \
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LE_BITS_TO_4BYTE(((__pcmdfbhdr) + 4), 16, 4)
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#define GET_C2H_CMD_FEEDBACK_CCX_SEQ(__pcmdfbhdr) \
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LE_BITS_TO_4BYTE(((__pcmdfbhdr) + 4), 20, 12)
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enum version_8192d {
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VERSION_TEST_CHIP_88C = 0x0000,
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VERSION_TEST_CHIP_92C = 0x0020,
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VERSION_TEST_UMC_CHIP_8723 = 0x0081,
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VERSION_NORMAL_TSMC_CHIP_88C = 0x0008,
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VERSION_NORMAL_TSMC_CHIP_92C = 0x0028,
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VERSION_NORMAL_TSMC_CHIP_92C_1T2R = 0x0018,
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VERSION_NORMAL_UMC_CHIP_88C_A_CUT = 0x0088,
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VERSION_NORMAL_UMC_CHIP_92C_A_CUT = 0x00a8,
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VERSION_NORMAL_UMC_CHIP_92C_1T2R_A_CUT = 0x0098,
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VERSION_NORMAL_UMC_CHIP_8723_1T1R_A_CUT = 0x0089,
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VERSION_NORMAL_UMC_CHIP_8723_1T1R_B_CUT = 0x1089,
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VERSION_NORMAL_UMC_CHIP_88C_B_CUT = 0x1088,
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VERSION_NORMAL_UMC_CHIP_92C_B_CUT = 0x10a8,
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VERSION_NORMAL_UMC_CHIP_92C_1T2R_B_CUT = 0x1090,
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VERSION_TEST_CHIP_92D_SINGLEPHY = 0x0022,
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VERSION_TEST_CHIP_92D_DUALPHY = 0x0002,
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VERSION_NORMAL_CHIP_92D_SINGLEPHY = 0x002a,
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VERSION_NORMAL_CHIP_92D_DUALPHY = 0x000a,
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VERSION_NORMAL_CHIP_92D_C_CUT_SINGLEPHY = 0x202a,
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VERSION_NORMAL_CHIP_92D_C_CUT_DUALPHY = 0x200a,
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VERSION_NORMAL_CHIP_92D_D_CUT_SINGLEPHY = 0x302a,
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VERSION_NORMAL_CHIP_92D_D_CUT_DUALPHY = 0x300a,
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VERSION_NORMAL_CHIP_92D_E_CUT_SINGLEPHY = 0x402a,
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VERSION_NORMAL_CHIP_92D_E_CUT_DUALPHY = 0x400a,
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};
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/* for 92D */
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#define CHIP_92D_SINGLEPHY BIT(9)
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/* Chip specific */
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#define CHIP_BONDING_IDENTIFIER(_value) (((_value)>>22)&0x3)
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#define CHIP_BONDING_92C_1T2R 0x1
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#define CHIP_BONDING_88C_USB_MCARD 0x2
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#define CHIP_BONDING_88C_USB_HP 0x1
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/* [15:12] IC version(CUT): A-cut=0, B-cut=1, C-cut=2, D-cut=3 */
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/* [7] Manufacturer: TSMC=0, UMC=1 */
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/* [6:4] RF type: 1T1R=0, 1T2R=1, 2T2R=2 */
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/* [3] Chip type: TEST=0, NORMAL=1 */
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/* [2:0] IC type: 81xxC=0, 8723=1, 92D=2 */
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#define CHIP_8723 BIT(0)
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#define CHIP_92D BIT(1)
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#define NORMAL_CHIP BIT(3)
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#define RF_TYPE_1T1R (~(BIT(4)|BIT(5)|BIT(6)))
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#define RF_TYPE_1T2R BIT(4)
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#define RF_TYPE_2T2R BIT(5)
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#define CHIP_VENDOR_UMC BIT(7)
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#define CHIP_92D_B_CUT BIT(12)
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#define CHIP_92D_C_CUT BIT(13)
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#define CHIP_92D_D_CUT (BIT(13)|BIT(12))
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#define CHIP_92D_E_CUT BIT(14)
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/* MASK */
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#define IC_TYPE_MASK (BIT(0)|BIT(1)|BIT(2))
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#define CHIP_TYPE_MASK BIT(3)
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#define RF_TYPE_MASK (BIT(4)|BIT(5)|BIT(6))
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#define MANUFACTUER_MASK BIT(7)
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#define ROM_VERSION_MASK (BIT(11)|BIT(10)|BIT(9)|BIT(8))
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#define CUT_VERSION_MASK (BIT(15)|BIT(14)|BIT(13)|BIT(12))
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/* Get element */
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#define GET_CVID_IC_TYPE(version) ((version) & IC_TYPE_MASK)
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#define GET_CVID_CHIP_TYPE(version) ((version) & CHIP_TYPE_MASK)
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#define GET_CVID_RF_TYPE(version) ((version) & RF_TYPE_MASK)
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#define GET_CVID_MANUFACTUER(version) ((version) & MANUFACTUER_MASK)
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#define GET_CVID_ROM_VERSION(version) ((version) & ROM_VERSION_MASK)
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#define GET_CVID_CUT_VERSION(version) ((version) & CUT_VERSION_MASK)
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#define IS_1T1R(version) ((GET_CVID_RF_TYPE(version)) ? \
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false : true)
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#define IS_1T2R(version) ((GET_CVID_RF_TYPE(version) == \
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RF_TYPE_1T2R) ? true : false)
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#define IS_2T2R(version) ((GET_CVID_RF_TYPE(version) == \
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RF_TYPE_2T2R) ? true : false)
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#define IS_92D_SINGLEPHY(version) ((IS_92D(version)) ? \
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(IS_2T2R(version) ? true : false) : false)
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#define IS_92D(version) ((GET_CVID_IC_TYPE(version) == \
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CHIP_92D) ? true : false)
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#define IS_92D_C_CUT(version) ((IS_92D(version)) ? \
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((GET_CVID_CUT_VERSION(version) == \
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CHIP_92D_C_CUT) ? true : false) : false)
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#define IS_92D_D_CUT(version) ((IS_92D(version)) ? \
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((GET_CVID_CUT_VERSION(version) == \
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CHIP_92D_D_CUT) ? true : false) : false)
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#define IS_92D_E_CUT(version) ((IS_92D(version)) ? \
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((GET_CVID_CUT_VERSION(version) == \
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CHIP_92D_E_CUT) ? true : false) : false)
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enum rf_optype {
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RF_OP_BY_SW_3WIRE = 0,
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RF_OP_BY_FW,
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RF_OP_MAX
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};
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enum rtl_desc_qsel {
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QSLT_BK = 0x2,
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QSLT_BE = 0x0,
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QSLT_VI = 0x5,
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QSLT_VO = 0x7,
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QSLT_BEACON = 0x10,
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QSLT_HIGH = 0x11,
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QSLT_MGNT = 0x12,
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QSLT_CMD = 0x13,
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};
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enum channel_plan {
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CHPL_FCC = 0,
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CHPL_IC = 1,
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CHPL_ETSI = 2,
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CHPL_SPAIN = 3,
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CHPL_FRANCE = 4,
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CHPL_MKK = 5,
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CHPL_MKK1 = 6,
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CHPL_ISRAEL = 7,
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CHPL_TELEC = 8,
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CHPL_GLOBAL = 9,
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CHPL_WORLD = 10,
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};
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struct phy_sts_cck_8192d {
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u8 adc_pwdb_X[4];
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u8 sq_rpt;
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u8 cck_agc_rpt;
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};
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struct h2c_cmd_8192c {
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u8 element_id;
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u32 cmd_len;
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u8 *p_cmdbuffer;
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};
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struct txpower_info {
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u8 cck_index[RF6052_MAX_PATH][CHANNEL_GROUP_MAX];
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u8 ht40_1sindex[RF6052_MAX_PATH][CHANNEL_GROUP_MAX];
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u8 ht40_2sindexdiff[RF6052_MAX_PATH][CHANNEL_GROUP_MAX];
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u8 ht20indexdiff[RF6052_MAX_PATH][CHANNEL_GROUP_MAX];
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u8 ofdmindexdiff[RF6052_MAX_PATH][CHANNEL_GROUP_MAX];
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u8 ht40maxoffset[RF6052_MAX_PATH][CHANNEL_GROUP_MAX];
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u8 ht20maxoffset[RF6052_MAX_PATH][CHANNEL_GROUP_MAX];
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u8 tssi_a[3]; /* 5GL/5GM/5GH */
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u8 tssi_b[3];
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};
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#endif
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