391 lines
13 KiB
C
391 lines
13 KiB
C
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/*
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* Copyright (c) 2004-2010 Atheros Communications Inc.
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* Copyright (c) 2011 Qualcomm Atheros, Inc.
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*/
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#ifndef TARGET_H
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#define TARGET_H
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#define AR6003_BOARD_DATA_SZ 1024
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#define AR6003_BOARD_EXT_DATA_SZ 768
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#define AR6003_BOARD_EXT_DATA_SZ_V2 1024
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#define AR6004_BOARD_DATA_SZ 6144
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#define AR6004_BOARD_EXT_DATA_SZ 0
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#define RESET_CONTROL_ADDRESS 0x00000000
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#define RESET_CONTROL_COLD_RST 0x00000100
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#define RESET_CONTROL_MBOX_RST 0x00000004
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#define CPU_CLOCK_STANDARD_S 0
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#define CPU_CLOCK_STANDARD 0x00000003
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#define CPU_CLOCK_ADDRESS 0x00000020
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#define CLOCK_CONTROL_ADDRESS 0x00000028
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#define CLOCK_CONTROL_LF_CLK32_S 2
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#define CLOCK_CONTROL_LF_CLK32 0x00000004
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#define SYSTEM_SLEEP_ADDRESS 0x000000c4
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#define SYSTEM_SLEEP_DISABLE_S 0
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#define SYSTEM_SLEEP_DISABLE 0x00000001
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#define LPO_CAL_ADDRESS 0x000000e0
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#define LPO_CAL_ENABLE_S 20
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#define LPO_CAL_ENABLE 0x00100000
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#define GPIO_PIN9_ADDRESS 0x0000004c
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#define GPIO_PIN10_ADDRESS 0x00000050
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#define GPIO_PIN11_ADDRESS 0x00000054
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#define GPIO_PIN12_ADDRESS 0x00000058
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#define GPIO_PIN13_ADDRESS 0x0000005c
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#define HOST_INT_STATUS_ADDRESS 0x00000400
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#define HOST_INT_STATUS_ERROR_S 7
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#define HOST_INT_STATUS_ERROR 0x00000080
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#define HOST_INT_STATUS_CPU_S 6
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#define HOST_INT_STATUS_CPU 0x00000040
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#define HOST_INT_STATUS_COUNTER_S 4
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#define HOST_INT_STATUS_COUNTER 0x00000010
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#define CPU_INT_STATUS_ADDRESS 0x00000401
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#define ERROR_INT_STATUS_ADDRESS 0x00000402
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#define ERROR_INT_STATUS_WAKEUP_S 2
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#define ERROR_INT_STATUS_WAKEUP 0x00000004
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#define ERROR_INT_STATUS_RX_UNDERFLOW_S 1
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#define ERROR_INT_STATUS_RX_UNDERFLOW 0x00000002
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#define ERROR_INT_STATUS_TX_OVERFLOW_S 0
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#define ERROR_INT_STATUS_TX_OVERFLOW 0x00000001
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#define COUNTER_INT_STATUS_ADDRESS 0x00000403
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#define COUNTER_INT_STATUS_COUNTER_S 0
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#define COUNTER_INT_STATUS_COUNTER 0x000000ff
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#define RX_LOOKAHEAD_VALID_ADDRESS 0x00000405
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#define INT_STATUS_ENABLE_ADDRESS 0x00000418
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#define INT_STATUS_ENABLE_ERROR_S 7
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#define INT_STATUS_ENABLE_ERROR 0x00000080
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#define INT_STATUS_ENABLE_CPU_S 6
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#define INT_STATUS_ENABLE_CPU 0x00000040
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#define INT_STATUS_ENABLE_INT_S 5
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#define INT_STATUS_ENABLE_INT 0x00000020
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#define INT_STATUS_ENABLE_COUNTER_S 4
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#define INT_STATUS_ENABLE_COUNTER 0x00000010
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#define INT_STATUS_ENABLE_MBOX_DATA_S 0
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#define INT_STATUS_ENABLE_MBOX_DATA 0x0000000f
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#define CPU_INT_STATUS_ENABLE_ADDRESS 0x00000419
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#define CPU_INT_STATUS_ENABLE_BIT_S 0
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#define CPU_INT_STATUS_ENABLE_BIT 0x000000ff
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#define ERROR_STATUS_ENABLE_ADDRESS 0x0000041a
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#define ERROR_STATUS_ENABLE_RX_UNDERFLOW_S 1
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#define ERROR_STATUS_ENABLE_RX_UNDERFLOW 0x00000002
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#define ERROR_STATUS_ENABLE_TX_OVERFLOW_S 0
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#define ERROR_STATUS_ENABLE_TX_OVERFLOW 0x00000001
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#define COUNTER_INT_STATUS_ENABLE_ADDRESS 0x0000041b
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#define COUNTER_INT_STATUS_ENABLE_BIT_S 0
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#define COUNTER_INT_STATUS_ENABLE_BIT 0x000000ff
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#define COUNT_ADDRESS 0x00000420
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#define COUNT_DEC_ADDRESS 0x00000440
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#define WINDOW_DATA_ADDRESS 0x00000474
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#define WINDOW_WRITE_ADDR_ADDRESS 0x00000478
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#define WINDOW_READ_ADDR_ADDRESS 0x0000047c
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#define CPU_DBG_SEL_ADDRESS 0x00000483
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#define CPU_DBG_ADDRESS 0x00000484
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#define LOCAL_SCRATCH_ADDRESS 0x000000c0
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#define ATH6KL_OPTION_SLEEP_DISABLE 0x08
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#define RTC_BASE_ADDRESS 0x00004000
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#define GPIO_BASE_ADDRESS 0x00014000
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#define MBOX_BASE_ADDRESS 0x00018000
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#define ANALOG_INTF_BASE_ADDRESS 0x0001c000
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#define WLAN_BOOTSTRAP_ADDRESS 0x00014140
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#define BOOTSTRAP_IS_HSIC(v) ((v) & (1 << 10))
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#define BOOTSTRAP_IS_USB(v) ((v) & (1 << 11))
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/* real name of the register is unknown */
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#define ATH6KL_ANALOG_PLL_REGISTER (ANALOG_INTF_BASE_ADDRESS + 0x284)
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#define SM(f, v) (((v) << f##_S) & f)
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#define MS(f, v) (((v) & f) >> f##_S)
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/*
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* xxx_HOST_INTEREST_ADDRESS is the address in Target RAM of the
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* host_interest structure.
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*
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* Host Interest is shared between Host and Target in order to coordinate
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* between the two, and is intended to remain constant (with additions only
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* at the end).
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*/
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#define ATH6KL_AR6003_HI_START_ADDR 0x00540600
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#define ATH6KL_AR6004_HI_START_ADDR 0x00400800
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/*
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* These are items that the Host may need to access
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* via BMI or via the Diagnostic Window. The position
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* of items in this structure must remain constant.
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* across firmware revisions!
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*
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* Types for each item must be fixed size across target and host platforms.
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* The structure is used only to calculate offset for each register with
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* HI_ITEM() macro, no values are stored to it.
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*
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* More items may be added at the end.
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*/
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struct host_interest {
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/*
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* Pointer to application-defined area, if any.
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* Set by Target application during startup.
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*/
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u32 hi_app_host_interest; /* 0x00 */
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/* Pointer to register dump area, valid after Target crash. */
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u32 hi_failure_state; /* 0x04 */
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/* Pointer to debug logging header */
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u32 hi_dbglog_hdr; /* 0x08 */
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u32 hi_unused1; /* 0x0c */
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/*
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* General-purpose flag bits, similar to ATH6KL_OPTION_* flags.
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* Can be used by application rather than by OS.
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*/
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u32 hi_option_flag; /* 0x10 */
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/*
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* Boolean that determines whether or not to
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* display messages on the serial port.
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*/
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u32 hi_serial_enable; /* 0x14 */
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/* Start address of DataSet index, if any */
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u32 hi_dset_list_head; /* 0x18 */
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/* Override Target application start address */
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u32 hi_app_start; /* 0x1c */
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/* Clock and voltage tuning */
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u32 hi_skip_clock_init; /* 0x20 */
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u32 hi_core_clock_setting; /* 0x24 */
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u32 hi_cpu_clock_setting; /* 0x28 */
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u32 hi_system_sleep_setting; /* 0x2c */
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u32 hi_xtal_control_setting; /* 0x30 */
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u32 hi_pll_ctrl_setting_24ghz; /* 0x34 */
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u32 hi_pll_ctrl_setting_5ghz; /* 0x38 */
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u32 hi_ref_voltage_trim_setting; /* 0x3c */
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u32 hi_clock_info; /* 0x40 */
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/*
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* Flash configuration overrides, used only
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* when firmware is not executing from flash.
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* (When using flash, modify the global variables
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* with equivalent names.)
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*/
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u32 hi_bank0_addr_value; /* 0x44 */
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u32 hi_bank0_read_value; /* 0x48 */
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u32 hi_bank0_write_value; /* 0x4c */
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u32 hi_bank0_config_value; /* 0x50 */
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/* Pointer to Board Data */
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u32 hi_board_data; /* 0x54 */
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u32 hi_board_data_initialized; /* 0x58 */
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u32 hi_dset_ram_index_tbl; /* 0x5c */
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u32 hi_desired_baud_rate; /* 0x60 */
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u32 hi_dbglog_config; /* 0x64 */
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u32 hi_end_ram_reserve_sz; /* 0x68 */
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u32 hi_mbox_io_block_sz; /* 0x6c */
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u32 hi_num_bpatch_streams; /* 0x70 -- unused */
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u32 hi_mbox_isr_yield_limit; /* 0x74 */
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u32 hi_refclk_hz; /* 0x78 */
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u32 hi_ext_clk_detected; /* 0x7c */
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u32 hi_dbg_uart_txpin; /* 0x80 */
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u32 hi_dbg_uart_rxpin; /* 0x84 */
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u32 hi_hci_uart_baud; /* 0x88 */
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u32 hi_hci_uart_pin_assignments; /* 0x8C */
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/*
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* NOTE: byte [0] = tx pin, [1] = rx pin, [2] = rts pin, [3] = cts
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* pin
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*/
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u32 hi_hci_uart_baud_scale_val; /* 0x90 */
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u32 hi_hci_uart_baud_step_val; /* 0x94 */
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u32 hi_allocram_start; /* 0x98 */
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u32 hi_allocram_sz; /* 0x9c */
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u32 hi_hci_bridge_flags; /* 0xa0 */
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u32 hi_hci_uart_support_pins; /* 0xa4 */
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/*
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* NOTE: byte [0] = RESET pin (bit 7 is polarity),
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* bytes[1]..bytes[3] are for future use
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*/
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u32 hi_hci_uart_pwr_mgmt_params; /* 0xa8 */
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/*
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* 0xa8 - [1]: 0 = UART FC active low, 1 = UART FC active high
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* [31:16]: wakeup timeout in ms
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*/
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/* Pointer to extended board data */
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u32 hi_board_ext_data; /* 0xac */
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u32 hi_board_ext_data_config; /* 0xb0 */
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/*
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* Bit [0] : valid
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* Bit[31:16: size
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*/
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/*
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* hi_reset_flag is used to do some stuff when target reset.
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* such as restore app_start after warm reset or
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* preserve host Interest area, or preserve ROM data, literals etc.
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*/
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u32 hi_reset_flag; /* 0xb4 */
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/* indicate hi_reset_flag is valid */
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u32 hi_reset_flag_valid; /* 0xb8 */
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u32 hi_hci_uart_pwr_mgmt_params_ext; /* 0xbc */
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/*
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* 0xbc - [31:0]: idle timeout in ms
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*/
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/* ACS flags */
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u32 hi_acs_flags; /* 0xc0 */
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u32 hi_console_flags; /* 0xc4 */
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u32 hi_nvram_state; /* 0xc8 */
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u32 hi_option_flag2; /* 0xcc */
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/* If non-zero, override values sent to Host in WMI_READY event. */
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u32 hi_sw_version_override; /* 0xd0 */
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u32 hi_abi_version_override; /* 0xd4 */
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/*
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* Percentage of high priority RX traffic to total expected RX traffic -
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* applicable only to ar6004
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*/
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u32 hi_hp_rx_traffic_ratio; /* 0xd8 */
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/* test applications flags */
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u32 hi_test_apps_related ; /* 0xdc */
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/* location of test script */
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u32 hi_ota_testscript; /* 0xe0 */
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/* location of CAL data */
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u32 hi_cal_data; /* 0xe4 */
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/* Number of packet log buffers */
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u32 hi_pktlog_num_buffers; /* 0xe8 */
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/* wow extension configuration */
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u32 hi_wow_ext_config; /* 0xec */
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u32 hi_pwr_save_flags; /* 0xf0 */
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} __packed;
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#define HI_ITEM(item) offsetof(struct host_interest, item)
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#define HI_OPTION_MAC_ADDR_METHOD_SHIFT 3
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#define HI_OPTION_FW_MODE_IBSS 0x0
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#define HI_OPTION_FW_MODE_BSS_STA 0x1
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#define HI_OPTION_FW_MODE_AP 0x2
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#define HI_OPTION_FW_SUBMODE_NONE 0x0
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#define HI_OPTION_FW_SUBMODE_P2PDEV 0x1
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#define HI_OPTION_FW_SUBMODE_P2PCLIENT 0x2
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#define HI_OPTION_FW_SUBMODE_P2PGO 0x3
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/* hi_option_flag2 options: Disable MAC address overwrite via OTP Feature */
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#define HI_OPTION_DISABLE_MAC_OTP 0x40
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#define HI_OPTION_NUM_DEV_SHIFT 0x9
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#define HI_OPTION_FW_BRIDGE_SHIFT 0x04
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/* Fw Mode/SubMode Mask
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|------------------------------------------------------------------------------|
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| SUB | SUB | SUB | SUB | | | |
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| MODE[3] | MODE[2] | MODE[1] | MODE[0] | MODE[3] | MODE[2] | MODE[1] | MODE[0|
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| (2) | (2) | (2) | (2) | (2) | (2) | (2) | (2)
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|------------------------------------------------------------------------------|
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*/
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#define HI_OPTION_FW_MODE_BITS 0x2
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#define HI_OPTION_FW_MODE_SHIFT 0xC
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#define HI_OPTION_FW_SUBMODE_BITS 0x2
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#define HI_OPTION_FW_SUBMODE_SHIFT 0x14
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/* hi_option_flag2 options */
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#define AMSDU_SLICING_OFFLOAD_TO_FW 0x1
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|
|
#define HI_OPTION_BAM2BAM_MODE 0x800000 /* Enable BAM2BAM mode */
|
||
|
|
|
||
|
|
/* hi_option_flag2 bit fields */
|
||
|
|
#define HI_OPTION_AP_CLIENT_CNT 0x3c00 /* max number of clients supportedAP mode */
|
||
|
|
|
||
|
|
/* hi_option_flag2 mask & shift count */
|
||
|
|
#define HI_OPTION_AP_CLIENT_CNT_SHIFT 0xA
|
||
|
|
/* 4-bits(bit13-bit10) to notify number of clients in AP mode */
|
||
|
|
#define HI_OPTION_AP_CLIENT_CNT_MASK 0xF
|
||
|
|
/* Enable Multichannel Concurrency (MCC) */
|
||
|
|
#define HI_OPTION_MCC_ENABLE 0x80000000
|
||
|
|
|
||
|
|
/*power save flag bit definitions*/
|
||
|
|
#define HI_PWR_SAVE_LPL_ENABLED 0x1
|
||
|
|
|
||
|
|
/* power save mode - reduced power listen */
|
||
|
|
#define HI_PWR_SAVE_LPL_DEV_MASK 0x3
|
||
|
|
#define HI_PWR_SAVE_LPL_DEV0_LSB 4
|
||
|
|
|
||
|
|
|
||
|
|
/* Convert a Target virtual address into a Target physical address */
|
||
|
|
#define AR6003_VTOP(vaddr) ((vaddr) & 0x001fffff)
|
||
|
|
#define AR6004_VTOP(vaddr) (vaddr)
|
||
|
|
|
||
|
|
#define TARG_VTOP(target_type, vaddr) \
|
||
|
|
(((target_type) == TARGET_TYPE_AR6003) ? AR6003_VTOP(vaddr) : \
|
||
|
|
(((target_type) == TARGET_TYPE_AR6004) ? AR6004_VTOP(vaddr) : 0))
|
||
|
|
|
||
|
|
#define ATH6KL_FWLOG_PAYLOAD_SIZE 1500
|
||
|
|
|
||
|
|
struct ath6kl_dbglog_buf {
|
||
|
|
__le32 next;
|
||
|
|
__le32 buffer_addr;
|
||
|
|
__le32 bufsize;
|
||
|
|
__le32 length;
|
||
|
|
__le32 count;
|
||
|
|
__le32 free;
|
||
|
|
} __packed;
|
||
|
|
|
||
|
|
struct ath6kl_dbglog_hdr {
|
||
|
|
__le32 dbuf_addr;
|
||
|
|
__le32 dropped;
|
||
|
|
} __packed;
|
||
|
|
|
||
|
|
#endif
|