255 lines
8.0 KiB
C
255 lines
8.0 KiB
C
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/* Copyright (c) 2012-2013, The Linux Foundation. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met:
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* * Redistributions in binary form must reproduce the above
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* copyright notice, this list of conditions and the following
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* disclaimer in the documentation and/or other materials provided
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* with the distribution.
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* * Neither the name of The Linux Foundation nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NON-INFRINGEMENT ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
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* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
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* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
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* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
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* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
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* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <debug.h>
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#include <platform.h>
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#include <qgic.h>
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#include <qtimer.h>
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#include <board.h>
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#include <qpic_nand.h>
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#include <mmu.h>
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#include <arch/arm/mmu.h>
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#include <platform/iomap.h>
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#include <target.h>
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#include <smem.h>
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#include <reg.h>
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#include <board.h>
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#include <boot_stats.h>
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extern struct smem_ram_ptable* target_smem_ram_ptable_init();
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#define MB (1024*1024)
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#define MSM_IOMAP_SIZE ((MSM_IOMAP_END - MSM_IOMAP_BASE)/MB)
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/* LK memory - Strongly ordered, executable */
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#define LK_MEMORY (MMU_MEMORY_TYPE_NORMAL | \
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MMU_MEMORY_AP_READ_WRITE)
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/* Scratch memory - Strongly ordered, non-executable */
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#define SCRATCH_MEMORY (MMU_MEMORY_TYPE_NORMAL | \
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MMU_MEMORY_AP_READ_WRITE | MMU_MEMORY_XN)
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/* Peripherals - shared device */
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#define IOMAP_MEMORY (MMU_MEMORY_TYPE_DEVICE_SHARED | \
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MMU_MEMORY_AP_READ_WRITE | MMU_MEMORY_XN)
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#define SCRATCH_REGION1_VIRT_START SCRATCH_REGION1
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#define SCRATCH_REGION2_VIRT_START (SCRATCH_REGION1_VIRT_START + \
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(SCRATCH_REGION1_SIZE))
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#define SDRAM_BANK0_LAST_FIXED_ADDR (SCRATCH_REGION2 + SCRATCH_REGION2_SIZE)
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/* Map all the accesssible memory according to the following rules:
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* 1. Map 1MB from MSM_SHARED_BASE with 1 -1 mapping.
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* 2. Map MEMBASE - MEMSIZE with 1 -1 mapping.
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* 3. Map all the scratch regions immediately after Appsbl memory.
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* Virtual addresses start right after Appsbl Virtual address.
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* 4. Map all the IOMAP space with 1 - 1 mapping.
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* 5. Map all the rest of the SDRAM/ IMEM regions as 1 -1.
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*/
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mmu_section_t mmu_section_table[] = {
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/* Physical addr, Virtual addr, Size (in MB), Flags */
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{MSM_SHARED_BASE, MSM_SHARED_BASE, 1, SCRATCH_MEMORY},
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{MEMBASE, MEMBASE, MEMSIZE / MB, LK_MEMORY},
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{SCRATCH_REGION1, SCRATCH_REGION1_VIRT_START, SCRATCH_REGION1_SIZE / MB, SCRATCH_MEMORY},
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{SCRATCH_REGION2, SCRATCH_REGION2_VIRT_START, SCRATCH_REGION2_SIZE / MB, SCRATCH_MEMORY},
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{MSM_IOMAP_BASE, MSM_IOMAP_BASE, MSM_IOMAP_SIZE, IOMAP_MEMORY},
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};
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/* Boot timestamps */
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#define BS_INFO_OFFSET (0x6B0)
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#define BS_INFO_ADDR_V1 (MSM_SHARED_IMEM_BASE + BS_INFO_OFFSET)
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#define BS_INFO_ADDR_V2 (MSM_SHARED_IMEM_BASE_V2 + BS_INFO_OFFSET)
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void platform_early_init(void)
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{
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/* Initialize board identifier data */
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board_init();
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/* Initialize clock driver */
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platform_clock_init();
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/* Initialize interrupt controller */
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qgic_init();
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/* timer */
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qtimer_init();
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}
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void platform_init(void)
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{
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dprintf(INFO, "platform_init()\n");
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}
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static uint32_t platform_get_sclk_count(void)
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{
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return readl(MPM2_MPM_SLEEP_TIMETICK_COUNT_VAL);
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}
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static uint32_t kernel_load_start;
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void bs_set_timestamp(enum bs_entry bs_id)
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{
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void *bs_imem;
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uint32_t soc_ver = board_soc_version();
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if (bs_id >= BS_MAX) {
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dprintf(CRITICAL, "bad bs id: %u, max: %u\n", bs_id, BS_MAX);
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ASSERT(0);
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}
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if (bs_id == BS_KERNEL_LOAD_START) {
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kernel_load_start = platform_get_sclk_count();
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return;
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}
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if (soc_ver < BOARD_SOC_VERSION2)
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bs_imem = (void *)BS_INFO_ADDR_V1;
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else
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bs_imem = (void *)BS_INFO_ADDR_V2;
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if(bs_id == BS_KERNEL_LOAD_DONE)
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writel(platform_get_sclk_count() - kernel_load_start,
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bs_imem + (sizeof(uint32_t) * BS_KERNEL_LOAD_TIME));
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else
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writel(platform_get_sclk_count(),
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bs_imem + (sizeof(uint32_t) * bs_id));
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}
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void platform_uninit(void)
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{
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qtimer_uninit();
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qpic_nand_uninit();
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}
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void platform_init_mmu_mappings(void)
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{
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struct smem_ram_ptable *ram_ptable;
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uint32_t i;
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uint32_t sections;
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uint32_t table_size = ARRAY_SIZE(mmu_section_table);
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uint32_t last_fixed_addr = SDRAM_BANK0_LAST_FIXED_ADDR;
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ram_ptable = target_smem_ram_ptable_init();
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/* Configure the MMU page entries for SDRAM and IMEM memory read
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from the smem ram table*/
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for(i = 0; i < ram_ptable->len; i++)
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{
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if((ram_ptable->parts[i].category == IMEM) || (ram_ptable->parts[i].category == SDRAM))
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{
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/* First bank info is added according to the static table - mmu_section_table. */
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if((ram_ptable->parts[i].start <= last_fixed_addr) &&
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((ram_ptable->parts[i].start + ram_ptable->parts[i].size) >= last_fixed_addr))
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continue;
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/* Check to ensure that start address is 1MB aligned */
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ASSERT((ram_ptable->parts[i].start & 0xFFFFF) == 0);
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sections = (ram_ptable->parts[i].size) / MB;
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while(sections--)
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{
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arm_mmu_map_section(ram_ptable->parts[i].start + sections * MB,
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ram_ptable->parts[i].start + sections * MB,
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SCRATCH_MEMORY);
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}
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}
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}
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/* Configure the MMU page entries for memory read from the
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mmu_section_table */
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for (i = 0; i < table_size; i++)
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{
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sections = mmu_section_table[i].num_of_sections;
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while (sections--)
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{
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arm_mmu_map_section(mmu_section_table[i].paddress + sections * MB,
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mmu_section_table[i].vaddress + sections * MB,
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mmu_section_table[i].flags);
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}
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}
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}
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addr_t platform_get_virt_to_phys_mapping(addr_t virt_addr)
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{
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uint32_t paddr;
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uint32_t table_size = ARRAY_SIZE(mmu_section_table);
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uint32_t limit;
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for (uint32_t i = 0; i < table_size; i++)
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{
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limit = (mmu_section_table[i].num_of_sections * MB) - 0x1;
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if (virt_addr >= mmu_section_table[i].vaddress &&
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virt_addr <= (mmu_section_table[i].vaddress + limit))
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{
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paddr = mmu_section_table[i].paddress + (virt_addr - mmu_section_table[i].vaddress);
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return paddr;
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}
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}
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/* No special mapping found.
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* Assume 1-1 mapping.
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*/
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paddr = virt_addr;
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return paddr;
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}
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addr_t platform_get_phys_to_virt_mapping(addr_t phys_addr)
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{
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uint32_t vaddr;
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uint32_t table_size = ARRAY_SIZE(mmu_section_table);
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uint32_t limit;
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for (uint32_t i = 0; i < table_size; i++)
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{
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limit = (mmu_section_table[i].num_of_sections * MB) - 0x1;
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if (phys_addr >= mmu_section_table[i].paddress &&
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phys_addr <= (mmu_section_table[i].paddress + limit))
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{
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vaddr = mmu_section_table[i].vaddress + (phys_addr - mmu_section_table[i].paddress);
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return vaddr;
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}
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}
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/* No special mapping found.
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* Assume 1-1 mapping.
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*/
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vaddr = phys_addr;
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return vaddr;
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}
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/* Do not use default identitiy mappings. */
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int platform_use_identity_mmu_mappings(void)
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{
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return 0;
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}
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