691 lines
18 KiB
C
691 lines
18 KiB
C
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/*
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* Freescale ALSA SoC Digital Audio Interface (SAI) driver.
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*
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* Copyright 2012-2013 Freescale Semiconductor, Inc.
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*
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* This program is free software, you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation, either version 2 of the License, or(at your
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* option) any later version.
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*
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*/
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#include <linux/clk.h>
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#include <linux/delay.h>
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#include <linux/dmaengine.h>
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#include <linux/module.h>
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#include <linux/of_address.h>
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#include <linux/regmap.h>
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#include <linux/slab.h>
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#include <sound/core.h>
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#include <sound/dmaengine_pcm.h>
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#include <sound/pcm_params.h>
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#include "fsl_sai.h"
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#include "imx-pcm.h"
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#define FSL_SAI_FLAGS (FSL_SAI_CSR_SEIE |\
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FSL_SAI_CSR_FEIE)
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static irqreturn_t fsl_sai_isr(int irq, void *devid)
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{
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struct fsl_sai *sai = (struct fsl_sai *)devid;
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struct device *dev = &sai->pdev->dev;
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u32 flags, xcsr, mask;
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bool irq_none = true;
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/*
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* Both IRQ status bits and IRQ mask bits are in the xCSR but
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* different shifts. And we here create a mask only for those
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* IRQs that we activated.
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*/
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mask = (FSL_SAI_FLAGS >> FSL_SAI_CSR_xIE_SHIFT) << FSL_SAI_CSR_xF_SHIFT;
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/* Tx IRQ */
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regmap_read(sai->regmap, FSL_SAI_TCSR, &xcsr);
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flags = xcsr & mask;
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if (flags)
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irq_none = false;
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else
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goto irq_rx;
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if (flags & FSL_SAI_CSR_WSF)
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dev_dbg(dev, "isr: Start of Tx word detected\n");
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if (flags & FSL_SAI_CSR_SEF)
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dev_warn(dev, "isr: Tx Frame sync error detected\n");
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if (flags & FSL_SAI_CSR_FEF) {
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dev_warn(dev, "isr: Transmit underrun detected\n");
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/* FIFO reset for safety */
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xcsr |= FSL_SAI_CSR_FR;
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}
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if (flags & FSL_SAI_CSR_FWF)
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dev_dbg(dev, "isr: Enabled transmit FIFO is empty\n");
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if (flags & FSL_SAI_CSR_FRF)
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dev_dbg(dev, "isr: Transmit FIFO watermark has been reached\n");
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flags &= FSL_SAI_CSR_xF_W_MASK;
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xcsr &= ~FSL_SAI_CSR_xF_MASK;
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if (flags)
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regmap_write(sai->regmap, FSL_SAI_TCSR, flags | xcsr);
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irq_rx:
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/* Rx IRQ */
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regmap_read(sai->regmap, FSL_SAI_RCSR, &xcsr);
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flags = xcsr & mask;
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if (flags)
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irq_none = false;
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else
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goto out;
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if (flags & FSL_SAI_CSR_WSF)
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dev_dbg(dev, "isr: Start of Rx word detected\n");
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if (flags & FSL_SAI_CSR_SEF)
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dev_warn(dev, "isr: Rx Frame sync error detected\n");
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if (flags & FSL_SAI_CSR_FEF) {
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dev_warn(dev, "isr: Receive overflow detected\n");
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/* FIFO reset for safety */
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xcsr |= FSL_SAI_CSR_FR;
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}
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if (flags & FSL_SAI_CSR_FWF)
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dev_dbg(dev, "isr: Enabled receive FIFO is full\n");
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if (flags & FSL_SAI_CSR_FRF)
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dev_dbg(dev, "isr: Receive FIFO watermark has been reached\n");
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flags &= FSL_SAI_CSR_xF_W_MASK;
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xcsr &= ~FSL_SAI_CSR_xF_MASK;
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if (flags)
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regmap_write(sai->regmap, FSL_SAI_RCSR, flags | xcsr);
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out:
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if (irq_none)
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return IRQ_NONE;
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else
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return IRQ_HANDLED;
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}
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static int fsl_sai_set_dai_sysclk_tr(struct snd_soc_dai *cpu_dai,
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int clk_id, unsigned int freq, int fsl_dir)
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{
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struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai);
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bool tx = fsl_dir == FSL_FMT_TRANSMITTER;
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u32 val_cr2 = 0;
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switch (clk_id) {
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case FSL_SAI_CLK_BUS:
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val_cr2 |= FSL_SAI_CR2_MSEL_BUS;
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break;
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case FSL_SAI_CLK_MAST1:
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val_cr2 |= FSL_SAI_CR2_MSEL_MCLK1;
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break;
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case FSL_SAI_CLK_MAST2:
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val_cr2 |= FSL_SAI_CR2_MSEL_MCLK2;
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break;
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case FSL_SAI_CLK_MAST3:
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val_cr2 |= FSL_SAI_CR2_MSEL_MCLK3;
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break;
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default:
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return -EINVAL;
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}
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regmap_update_bits(sai->regmap, FSL_SAI_xCR2(tx),
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FSL_SAI_CR2_MSEL_MASK, val_cr2);
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return 0;
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}
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static int fsl_sai_set_dai_sysclk(struct snd_soc_dai *cpu_dai,
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int clk_id, unsigned int freq, int dir)
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{
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int ret;
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if (dir == SND_SOC_CLOCK_IN)
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return 0;
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ret = fsl_sai_set_dai_sysclk_tr(cpu_dai, clk_id, freq,
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FSL_FMT_TRANSMITTER);
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if (ret) {
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dev_err(cpu_dai->dev, "Cannot set tx sysclk: %d\n", ret);
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return ret;
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}
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ret = fsl_sai_set_dai_sysclk_tr(cpu_dai, clk_id, freq,
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FSL_FMT_RECEIVER);
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if (ret)
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dev_err(cpu_dai->dev, "Cannot set rx sysclk: %d\n", ret);
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return ret;
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}
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static int fsl_sai_set_dai_fmt_tr(struct snd_soc_dai *cpu_dai,
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unsigned int fmt, int fsl_dir)
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{
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struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai);
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bool tx = fsl_dir == FSL_FMT_TRANSMITTER;
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u32 val_cr2 = 0, val_cr4 = 0;
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if (!sai->is_lsb_first)
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val_cr4 |= FSL_SAI_CR4_MF;
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/* DAI mode */
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switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
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case SND_SOC_DAIFMT_I2S:
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/*
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* Frame low, 1clk before data, one word length for frame sync,
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* frame sync starts one serial clock cycle earlier,
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* that is, together with the last bit of the previous
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* data word.
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*/
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val_cr2 |= FSL_SAI_CR2_BCP;
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val_cr4 |= FSL_SAI_CR4_FSE | FSL_SAI_CR4_FSP;
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break;
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case SND_SOC_DAIFMT_LEFT_J:
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/*
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* Frame high, one word length for frame sync,
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* frame sync asserts with the first bit of the frame.
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*/
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val_cr2 |= FSL_SAI_CR2_BCP;
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break;
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case SND_SOC_DAIFMT_DSP_A:
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/*
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* Frame high, 1clk before data, one bit for frame sync,
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* frame sync starts one serial clock cycle earlier,
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* that is, together with the last bit of the previous
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* data word.
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*/
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val_cr2 |= FSL_SAI_CR2_BCP;
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val_cr4 |= FSL_SAI_CR4_FSE;
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sai->is_dsp_mode = true;
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break;
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case SND_SOC_DAIFMT_DSP_B:
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/*
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* Frame high, one bit for frame sync,
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* frame sync asserts with the first bit of the frame.
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*/
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val_cr2 |= FSL_SAI_CR2_BCP;
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sai->is_dsp_mode = true;
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break;
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case SND_SOC_DAIFMT_RIGHT_J:
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/* To be done */
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default:
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return -EINVAL;
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}
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/* DAI clock inversion */
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switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
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case SND_SOC_DAIFMT_IB_IF:
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/* Invert both clocks */
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val_cr2 ^= FSL_SAI_CR2_BCP;
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val_cr4 ^= FSL_SAI_CR4_FSP;
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break;
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case SND_SOC_DAIFMT_IB_NF:
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/* Invert bit clock */
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val_cr2 ^= FSL_SAI_CR2_BCP;
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break;
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case SND_SOC_DAIFMT_NB_IF:
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/* Invert frame clock */
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val_cr4 ^= FSL_SAI_CR4_FSP;
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break;
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case SND_SOC_DAIFMT_NB_NF:
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/* Nothing to do for both normal cases */
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break;
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default:
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return -EINVAL;
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}
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/* DAI clock master masks */
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switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
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case SND_SOC_DAIFMT_CBS_CFS:
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val_cr2 |= FSL_SAI_CR2_BCD_MSTR;
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val_cr4 |= FSL_SAI_CR4_FSD_MSTR;
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break;
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case SND_SOC_DAIFMT_CBM_CFM:
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break;
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case SND_SOC_DAIFMT_CBS_CFM:
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val_cr2 |= FSL_SAI_CR2_BCD_MSTR;
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break;
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case SND_SOC_DAIFMT_CBM_CFS:
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val_cr4 |= FSL_SAI_CR4_FSD_MSTR;
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break;
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default:
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return -EINVAL;
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}
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regmap_update_bits(sai->regmap, FSL_SAI_xCR2(tx),
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FSL_SAI_CR2_BCP | FSL_SAI_CR2_BCD_MSTR, val_cr2);
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regmap_update_bits(sai->regmap, FSL_SAI_xCR4(tx),
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FSL_SAI_CR4_MF | FSL_SAI_CR4_FSE |
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FSL_SAI_CR4_FSP | FSL_SAI_CR4_FSD_MSTR, val_cr4);
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return 0;
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}
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static int fsl_sai_set_dai_fmt(struct snd_soc_dai *cpu_dai, unsigned int fmt)
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{
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int ret;
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ret = fsl_sai_set_dai_fmt_tr(cpu_dai, fmt, FSL_FMT_TRANSMITTER);
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if (ret) {
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dev_err(cpu_dai->dev, "Cannot set tx format: %d\n", ret);
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return ret;
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}
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ret = fsl_sai_set_dai_fmt_tr(cpu_dai, fmt, FSL_FMT_RECEIVER);
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if (ret)
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dev_err(cpu_dai->dev, "Cannot set rx format: %d\n", ret);
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return ret;
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}
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static int fsl_sai_hw_params(struct snd_pcm_substream *substream,
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struct snd_pcm_hw_params *params,
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struct snd_soc_dai *cpu_dai)
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{
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struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai);
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bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
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unsigned int channels = params_channels(params);
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u32 word_width = snd_pcm_format_width(params_format(params));
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u32 val_cr4 = 0, val_cr5 = 0;
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if (!sai->is_dsp_mode)
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val_cr4 |= FSL_SAI_CR4_SYWD(word_width);
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val_cr5 |= FSL_SAI_CR5_WNW(word_width);
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val_cr5 |= FSL_SAI_CR5_W0W(word_width);
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if (sai->is_lsb_first)
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val_cr5 |= FSL_SAI_CR5_FBT(0);
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else
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val_cr5 |= FSL_SAI_CR5_FBT(word_width - 1);
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val_cr4 |= FSL_SAI_CR4_FRSZ(channels);
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regmap_update_bits(sai->regmap, FSL_SAI_xCR4(tx),
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FSL_SAI_CR4_SYWD_MASK | FSL_SAI_CR4_FRSZ_MASK,
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val_cr4);
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regmap_update_bits(sai->regmap, FSL_SAI_xCR5(tx),
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FSL_SAI_CR5_WNW_MASK | FSL_SAI_CR5_W0W_MASK |
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FSL_SAI_CR5_FBT_MASK, val_cr5);
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regmap_write(sai->regmap, FSL_SAI_xMR(tx), ~0UL - ((1 << channels) - 1));
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return 0;
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}
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static int fsl_sai_trigger(struct snd_pcm_substream *substream, int cmd,
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struct snd_soc_dai *cpu_dai)
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{
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struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai);
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bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
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u32 xcsr, count = 100;
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/*
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* Asynchronous mode: Clear SYNC for both Tx and Rx.
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* Rx sync with Tx clocks: Clear SYNC for Tx, set it for Rx.
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* Tx sync with Rx clocks: Clear SYNC for Rx, set it for Tx.
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*/
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regmap_update_bits(sai->regmap, FSL_SAI_TCR2, FSL_SAI_CR2_SYNC, 0);
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regmap_update_bits(sai->regmap, FSL_SAI_RCR2, FSL_SAI_CR2_SYNC,
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sai->synchronous[RX] ? FSL_SAI_CR2_SYNC : 0);
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/*
|
||
|
|
* It is recommended that the transmitter is the last enabled
|
||
|
|
* and the first disabled.
|
||
|
|
*/
|
||
|
|
switch (cmd) {
|
||
|
|
case SNDRV_PCM_TRIGGER_START:
|
||
|
|
case SNDRV_PCM_TRIGGER_RESUME:
|
||
|
|
case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
|
||
|
|
regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx),
|
||
|
|
FSL_SAI_CSR_FRDE, FSL_SAI_CSR_FRDE);
|
||
|
|
|
||
|
|
regmap_update_bits(sai->regmap, FSL_SAI_RCSR,
|
||
|
|
FSL_SAI_CSR_TERE, FSL_SAI_CSR_TERE);
|
||
|
|
regmap_update_bits(sai->regmap, FSL_SAI_TCSR,
|
||
|
|
FSL_SAI_CSR_TERE, FSL_SAI_CSR_TERE);
|
||
|
|
|
||
|
|
regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx),
|
||
|
|
FSL_SAI_CSR_xIE_MASK, FSL_SAI_FLAGS);
|
||
|
|
break;
|
||
|
|
case SNDRV_PCM_TRIGGER_STOP:
|
||
|
|
case SNDRV_PCM_TRIGGER_SUSPEND:
|
||
|
|
case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
|
||
|
|
regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx),
|
||
|
|
FSL_SAI_CSR_FRDE, 0);
|
||
|
|
regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx),
|
||
|
|
FSL_SAI_CSR_xIE_MASK, 0);
|
||
|
|
|
||
|
|
/* Check if the opposite FRDE is also disabled */
|
||
|
|
regmap_read(sai->regmap, FSL_SAI_xCSR(!tx), &xcsr);
|
||
|
|
if (!(xcsr & FSL_SAI_CSR_FRDE)) {
|
||
|
|
/* Disable both directions and reset their FIFOs */
|
||
|
|
regmap_update_bits(sai->regmap, FSL_SAI_TCSR,
|
||
|
|
FSL_SAI_CSR_TERE, 0);
|
||
|
|
regmap_update_bits(sai->regmap, FSL_SAI_RCSR,
|
||
|
|
FSL_SAI_CSR_TERE, 0);
|
||
|
|
|
||
|
|
/* TERE will remain set till the end of current frame */
|
||
|
|
do {
|
||
|
|
udelay(10);
|
||
|
|
regmap_read(sai->regmap, FSL_SAI_xCSR(tx), &xcsr);
|
||
|
|
} while (--count && xcsr & FSL_SAI_CSR_TERE);
|
||
|
|
|
||
|
|
regmap_update_bits(sai->regmap, FSL_SAI_TCSR,
|
||
|
|
FSL_SAI_CSR_FR, FSL_SAI_CSR_FR);
|
||
|
|
regmap_update_bits(sai->regmap, FSL_SAI_RCSR,
|
||
|
|
FSL_SAI_CSR_FR, FSL_SAI_CSR_FR);
|
||
|
|
}
|
||
|
|
break;
|
||
|
|
default:
|
||
|
|
return -EINVAL;
|
||
|
|
}
|
||
|
|
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
|
||
|
|
static int fsl_sai_startup(struct snd_pcm_substream *substream,
|
||
|
|
struct snd_soc_dai *cpu_dai)
|
||
|
|
{
|
||
|
|
struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai);
|
||
|
|
bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
|
||
|
|
struct device *dev = &sai->pdev->dev;
|
||
|
|
int ret;
|
||
|
|
|
||
|
|
ret = clk_prepare_enable(sai->bus_clk);
|
||
|
|
if (ret) {
|
||
|
|
dev_err(dev, "failed to enable bus clock: %d\n", ret);
|
||
|
|
return ret;
|
||
|
|
}
|
||
|
|
|
||
|
|
regmap_update_bits(sai->regmap, FSL_SAI_xCR3(tx), FSL_SAI_CR3_TRCE,
|
||
|
|
FSL_SAI_CR3_TRCE);
|
||
|
|
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
|
||
|
|
static void fsl_sai_shutdown(struct snd_pcm_substream *substream,
|
||
|
|
struct snd_soc_dai *cpu_dai)
|
||
|
|
{
|
||
|
|
struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai);
|
||
|
|
bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
|
||
|
|
|
||
|
|
regmap_update_bits(sai->regmap, FSL_SAI_xCR3(tx), FSL_SAI_CR3_TRCE, 0);
|
||
|
|
|
||
|
|
clk_disable_unprepare(sai->bus_clk);
|
||
|
|
}
|
||
|
|
|
||
|
|
static const struct snd_soc_dai_ops fsl_sai_pcm_dai_ops = {
|
||
|
|
.set_sysclk = fsl_sai_set_dai_sysclk,
|
||
|
|
.set_fmt = fsl_sai_set_dai_fmt,
|
||
|
|
.hw_params = fsl_sai_hw_params,
|
||
|
|
.trigger = fsl_sai_trigger,
|
||
|
|
.startup = fsl_sai_startup,
|
||
|
|
.shutdown = fsl_sai_shutdown,
|
||
|
|
};
|
||
|
|
|
||
|
|
static int fsl_sai_dai_probe(struct snd_soc_dai *cpu_dai)
|
||
|
|
{
|
||
|
|
struct fsl_sai *sai = dev_get_drvdata(cpu_dai->dev);
|
||
|
|
|
||
|
|
/* Software Reset for both Tx and Rx */
|
||
|
|
regmap_write(sai->regmap, FSL_SAI_TCSR, FSL_SAI_CSR_SR);
|
||
|
|
regmap_write(sai->regmap, FSL_SAI_RCSR, FSL_SAI_CSR_SR);
|
||
|
|
/* Clear SR bit to finish the reset */
|
||
|
|
regmap_write(sai->regmap, FSL_SAI_TCSR, 0);
|
||
|
|
regmap_write(sai->regmap, FSL_SAI_RCSR, 0);
|
||
|
|
|
||
|
|
regmap_update_bits(sai->regmap, FSL_SAI_TCR1, FSL_SAI_CR1_RFW_MASK,
|
||
|
|
FSL_SAI_MAXBURST_TX * 2);
|
||
|
|
regmap_update_bits(sai->regmap, FSL_SAI_RCR1, FSL_SAI_CR1_RFW_MASK,
|
||
|
|
FSL_SAI_MAXBURST_RX - 1);
|
||
|
|
|
||
|
|
snd_soc_dai_init_dma_data(cpu_dai, &sai->dma_params_tx,
|
||
|
|
&sai->dma_params_rx);
|
||
|
|
|
||
|
|
snd_soc_dai_set_drvdata(cpu_dai, sai);
|
||
|
|
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
|
||
|
|
static struct snd_soc_dai_driver fsl_sai_dai = {
|
||
|
|
.probe = fsl_sai_dai_probe,
|
||
|
|
.playback = {
|
||
|
|
.stream_name = "CPU-Playback",
|
||
|
|
.channels_min = 1,
|
||
|
|
.channels_max = 2,
|
||
|
|
.rates = SNDRV_PCM_RATE_8000_96000,
|
||
|
|
.formats = FSL_SAI_FORMATS,
|
||
|
|
},
|
||
|
|
.capture = {
|
||
|
|
.stream_name = "CPU-Capture",
|
||
|
|
.channels_min = 1,
|
||
|
|
.channels_max = 2,
|
||
|
|
.rates = SNDRV_PCM_RATE_8000_96000,
|
||
|
|
.formats = FSL_SAI_FORMATS,
|
||
|
|
},
|
||
|
|
.ops = &fsl_sai_pcm_dai_ops,
|
||
|
|
};
|
||
|
|
|
||
|
|
static const struct snd_soc_component_driver fsl_component = {
|
||
|
|
.name = "fsl-sai",
|
||
|
|
};
|
||
|
|
|
||
|
|
static bool fsl_sai_readable_reg(struct device *dev, unsigned int reg)
|
||
|
|
{
|
||
|
|
switch (reg) {
|
||
|
|
case FSL_SAI_TCSR:
|
||
|
|
case FSL_SAI_TCR1:
|
||
|
|
case FSL_SAI_TCR2:
|
||
|
|
case FSL_SAI_TCR3:
|
||
|
|
case FSL_SAI_TCR4:
|
||
|
|
case FSL_SAI_TCR5:
|
||
|
|
case FSL_SAI_TFR:
|
||
|
|
case FSL_SAI_TMR:
|
||
|
|
case FSL_SAI_RCSR:
|
||
|
|
case FSL_SAI_RCR1:
|
||
|
|
case FSL_SAI_RCR2:
|
||
|
|
case FSL_SAI_RCR3:
|
||
|
|
case FSL_SAI_RCR4:
|
||
|
|
case FSL_SAI_RCR5:
|
||
|
|
case FSL_SAI_RDR:
|
||
|
|
case FSL_SAI_RFR:
|
||
|
|
case FSL_SAI_RMR:
|
||
|
|
return true;
|
||
|
|
default:
|
||
|
|
return false;
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
static bool fsl_sai_volatile_reg(struct device *dev, unsigned int reg)
|
||
|
|
{
|
||
|
|
switch (reg) {
|
||
|
|
case FSL_SAI_TFR:
|
||
|
|
case FSL_SAI_RFR:
|
||
|
|
case FSL_SAI_TDR:
|
||
|
|
case FSL_SAI_RDR:
|
||
|
|
return true;
|
||
|
|
default:
|
||
|
|
return false;
|
||
|
|
}
|
||
|
|
|
||
|
|
}
|
||
|
|
|
||
|
|
static bool fsl_sai_writeable_reg(struct device *dev, unsigned int reg)
|
||
|
|
{
|
||
|
|
switch (reg) {
|
||
|
|
case FSL_SAI_TCSR:
|
||
|
|
case FSL_SAI_TCR1:
|
||
|
|
case FSL_SAI_TCR2:
|
||
|
|
case FSL_SAI_TCR3:
|
||
|
|
case FSL_SAI_TCR4:
|
||
|
|
case FSL_SAI_TCR5:
|
||
|
|
case FSL_SAI_TDR:
|
||
|
|
case FSL_SAI_TMR:
|
||
|
|
case FSL_SAI_RCSR:
|
||
|
|
case FSL_SAI_RCR1:
|
||
|
|
case FSL_SAI_RCR2:
|
||
|
|
case FSL_SAI_RCR3:
|
||
|
|
case FSL_SAI_RCR4:
|
||
|
|
case FSL_SAI_RCR5:
|
||
|
|
case FSL_SAI_RMR:
|
||
|
|
return true;
|
||
|
|
default:
|
||
|
|
return false;
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
static const struct regmap_config fsl_sai_regmap_config = {
|
||
|
|
.reg_bits = 32,
|
||
|
|
.reg_stride = 4,
|
||
|
|
.val_bits = 32,
|
||
|
|
|
||
|
|
.max_register = FSL_SAI_RMR,
|
||
|
|
.readable_reg = fsl_sai_readable_reg,
|
||
|
|
.volatile_reg = fsl_sai_volatile_reg,
|
||
|
|
.writeable_reg = fsl_sai_writeable_reg,
|
||
|
|
};
|
||
|
|
|
||
|
|
static int fsl_sai_probe(struct platform_device *pdev)
|
||
|
|
{
|
||
|
|
struct device_node *np = pdev->dev.of_node;
|
||
|
|
struct fsl_sai *sai;
|
||
|
|
struct resource *res;
|
||
|
|
void __iomem *base;
|
||
|
|
char tmp[8];
|
||
|
|
int irq, ret, i;
|
||
|
|
|
||
|
|
sai = devm_kzalloc(&pdev->dev, sizeof(*sai), GFP_KERNEL);
|
||
|
|
if (!sai)
|
||
|
|
return -ENOMEM;
|
||
|
|
|
||
|
|
sai->pdev = pdev;
|
||
|
|
|
||
|
|
if (of_device_is_compatible(pdev->dev.of_node, "fsl,imx6sx-sai"))
|
||
|
|
sai->sai_on_imx = true;
|
||
|
|
|
||
|
|
sai->is_lsb_first = of_property_read_bool(np, "lsb-first");
|
||
|
|
|
||
|
|
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
||
|
|
base = devm_ioremap_resource(&pdev->dev, res);
|
||
|
|
if (IS_ERR(base))
|
||
|
|
return PTR_ERR(base);
|
||
|
|
|
||
|
|
sai->regmap = devm_regmap_init_mmio_clk(&pdev->dev,
|
||
|
|
"bus", base, &fsl_sai_regmap_config);
|
||
|
|
|
||
|
|
/* Compatible with old DTB cases */
|
||
|
|
if (IS_ERR(sai->regmap))
|
||
|
|
sai->regmap = devm_regmap_init_mmio_clk(&pdev->dev,
|
||
|
|
"sai", base, &fsl_sai_regmap_config);
|
||
|
|
if (IS_ERR(sai->regmap)) {
|
||
|
|
dev_err(&pdev->dev, "regmap init failed\n");
|
||
|
|
return PTR_ERR(sai->regmap);
|
||
|
|
}
|
||
|
|
|
||
|
|
/* No error out for old DTB cases but only mark the clock NULL */
|
||
|
|
sai->bus_clk = devm_clk_get(&pdev->dev, "bus");
|
||
|
|
if (IS_ERR(sai->bus_clk)) {
|
||
|
|
dev_err(&pdev->dev, "failed to get bus clock: %ld\n",
|
||
|
|
PTR_ERR(sai->bus_clk));
|
||
|
|
sai->bus_clk = NULL;
|
||
|
|
}
|
||
|
|
|
||
|
|
for (i = 0; i < FSL_SAI_MCLK_MAX; i++) {
|
||
|
|
sprintf(tmp, "mclk%d", i + 1);
|
||
|
|
sai->mclk_clk[i] = devm_clk_get(&pdev->dev, tmp);
|
||
|
|
if (IS_ERR(sai->mclk_clk[i])) {
|
||
|
|
dev_err(&pdev->dev, "failed to get mclk%d clock: %ld\n",
|
||
|
|
i + 1, PTR_ERR(sai->mclk_clk[i]));
|
||
|
|
sai->mclk_clk[i] = NULL;
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
irq = platform_get_irq(pdev, 0);
|
||
|
|
if (irq < 0) {
|
||
|
|
dev_err(&pdev->dev, "no irq for node %s\n", np->full_name);
|
||
|
|
return irq;
|
||
|
|
}
|
||
|
|
|
||
|
|
ret = devm_request_irq(&pdev->dev, irq, fsl_sai_isr, 0, np->name, sai);
|
||
|
|
if (ret) {
|
||
|
|
dev_err(&pdev->dev, "failed to claim irq %u\n", irq);
|
||
|
|
return ret;
|
||
|
|
}
|
||
|
|
|
||
|
|
/* Sync Tx with Rx as default by following old DT binding */
|
||
|
|
sai->synchronous[RX] = true;
|
||
|
|
sai->synchronous[TX] = false;
|
||
|
|
fsl_sai_dai.symmetric_rates = 1;
|
||
|
|
fsl_sai_dai.symmetric_channels = 1;
|
||
|
|
fsl_sai_dai.symmetric_samplebits = 1;
|
||
|
|
|
||
|
|
if (of_find_property(np, "fsl,sai-synchronous-rx", NULL) &&
|
||
|
|
of_find_property(np, "fsl,sai-asynchronous", NULL)) {
|
||
|
|
/* error out if both synchronous and asynchronous are present */
|
||
|
|
dev_err(&pdev->dev, "invalid binding for synchronous mode\n");
|
||
|
|
return -EINVAL;
|
||
|
|
}
|
||
|
|
|
||
|
|
if (of_find_property(np, "fsl,sai-synchronous-rx", NULL)) {
|
||
|
|
/* Sync Rx with Tx */
|
||
|
|
sai->synchronous[RX] = false;
|
||
|
|
sai->synchronous[TX] = true;
|
||
|
|
} else if (of_find_property(np, "fsl,sai-asynchronous", NULL)) {
|
||
|
|
/* Discard all settings for asynchronous mode */
|
||
|
|
sai->synchronous[RX] = false;
|
||
|
|
sai->synchronous[TX] = false;
|
||
|
|
fsl_sai_dai.symmetric_rates = 0;
|
||
|
|
fsl_sai_dai.symmetric_channels = 0;
|
||
|
|
fsl_sai_dai.symmetric_samplebits = 0;
|
||
|
|
}
|
||
|
|
|
||
|
|
sai->dma_params_rx.addr = res->start + FSL_SAI_RDR;
|
||
|
|
sai->dma_params_tx.addr = res->start + FSL_SAI_TDR;
|
||
|
|
sai->dma_params_rx.maxburst = FSL_SAI_MAXBURST_RX;
|
||
|
|
sai->dma_params_tx.maxburst = FSL_SAI_MAXBURST_TX;
|
||
|
|
|
||
|
|
platform_set_drvdata(pdev, sai);
|
||
|
|
|
||
|
|
ret = devm_snd_soc_register_component(&pdev->dev, &fsl_component,
|
||
|
|
&fsl_sai_dai, 1);
|
||
|
|
if (ret)
|
||
|
|
return ret;
|
||
|
|
|
||
|
|
if (sai->sai_on_imx)
|
||
|
|
return imx_pcm_dma_init(pdev);
|
||
|
|
else
|
||
|
|
return devm_snd_dmaengine_pcm_register(&pdev->dev, NULL,
|
||
|
|
SND_DMAENGINE_PCM_FLAG_NO_RESIDUE);
|
||
|
|
}
|
||
|
|
|
||
|
|
static const struct of_device_id fsl_sai_ids[] = {
|
||
|
|
{ .compatible = "fsl,vf610-sai", },
|
||
|
|
{ .compatible = "fsl,imx6sx-sai", },
|
||
|
|
{ /* sentinel */ }
|
||
|
|
};
|
||
|
|
|
||
|
|
static struct platform_driver fsl_sai_driver = {
|
||
|
|
.probe = fsl_sai_probe,
|
||
|
|
.driver = {
|
||
|
|
.name = "fsl-sai",
|
||
|
|
.owner = THIS_MODULE,
|
||
|
|
.of_match_table = fsl_sai_ids,
|
||
|
|
},
|
||
|
|
};
|
||
|
|
module_platform_driver(fsl_sai_driver);
|
||
|
|
|
||
|
|
MODULE_DESCRIPTION("Freescale Soc SAI Interface");
|
||
|
|
MODULE_AUTHOR("Xiubo Li, <Li.Xiubo@freescale.com>");
|
||
|
|
MODULE_ALIAS("platform:fsl-sai");
|
||
|
|
MODULE_LICENSE("GPL");
|