314 lines
8.6 KiB
C
314 lines
8.6 KiB
C
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/*
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* Copyright (c) 2013-2015, Linux Foundation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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* only version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*/
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#include "phy-qcom-ufs-qmp-14nm.h"
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#define UFS_PHY_NAME "ufs_phy_qmp_14nm"
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static
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int ufs_qcom_phy_qmp_14nm_phy_calibrate(struct ufs_qcom_phy *ufs_qcom_phy,
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bool is_rate_B)
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{
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int err;
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int tbl_size_A, tbl_size_B;
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struct ufs_qcom_phy_calibration *tbl_A, *tbl_B;
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u8 major = ufs_qcom_phy->host_ctrl_rev_major;
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u16 minor = ufs_qcom_phy->host_ctrl_rev_minor;
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u16 step = ufs_qcom_phy->host_ctrl_rev_step;
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tbl_size_B = ARRAY_SIZE(phy_cal_table_rate_B);
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tbl_B = phy_cal_table_rate_B;
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if ((major == 0x2) && (minor == 0x000) && (step == 0x0000)) {
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tbl_A = phy_cal_table_rate_A_2_0_0;
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tbl_size_A = ARRAY_SIZE(phy_cal_table_rate_A_2_0_0);
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} else if ((major == 0x2) && (minor == 0x001) && (step == 0x0000)) {
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tbl_A = phy_cal_table_rate_A_2_1_0;
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tbl_size_A = ARRAY_SIZE(phy_cal_table_rate_A_2_1_0);
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} else if ((major == 0x2) && (minor == 0x002) && (step == 0x0000)) {
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tbl_A = phy_cal_table_rate_A_2_2_0;
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tbl_size_A = ARRAY_SIZE(phy_cal_table_rate_A_2_2_0);
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tbl_B = phy_cal_table_rate_B_2_2_0;
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tbl_size_B = ARRAY_SIZE(phy_cal_table_rate_B_2_2_0);
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} else {
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dev_err(ufs_qcom_phy->dev,
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"%s: Unknown UFS-PHY version (major 0x%x minor 0x%x step 0x%x), no calibration values\n",
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__func__, major, minor, step);
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err = -ENODEV;
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goto out;
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}
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err = ufs_qcom_phy_calibrate(ufs_qcom_phy,
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tbl_A, tbl_size_A,
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tbl_B, tbl_size_B,
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is_rate_B);
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if (ufs_qcom_phy->quirks & UFS_QCOM_PHY_QUIRK_VCO_MANUAL_TUNING)
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writel_relaxed(ufs_qcom_phy->vco_tune1_mode1,
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ufs_qcom_phy->mmio + QSERDES_COM_VCO_TUNE1_MODE1);
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out:
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if (err)
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dev_err(ufs_qcom_phy->dev,
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"%s: ufs_qcom_phy_calibrate() failed %d\n",
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__func__, err);
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return err;
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}
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static
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void ufs_qcom_phy_qmp_14nm_advertise_quirks(struct ufs_qcom_phy *phy_common)
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{
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u8 major = phy_common->host_ctrl_rev_major;
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u16 minor = phy_common->host_ctrl_rev_minor;
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u16 step = phy_common->host_ctrl_rev_step;
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if ((major == 0x2) && (minor == 0x000) && (step == 0x0000))
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phy_common->quirks =
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UFS_QCOM_PHY_QUIRK_HIBERN8_EXIT_AFTER_PHY_PWR_COLLAPSE |
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UFS_QCOM_PHY_QUIRK_SVS_MODE |
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UFS_QCOM_PHY_QUIRK_VCO_MANUAL_TUNING;
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}
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static int ufs_qcom_phy_qmp_14nm_init(struct phy *generic_phy)
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{
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struct ufs_qcom_phy_qmp_14nm *phy = phy_get_drvdata(generic_phy);
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struct ufs_qcom_phy *phy_common = &phy->common_cfg;
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int err;
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err = ufs_qcom_phy_init_clks(generic_phy, phy_common);
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if (err) {
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dev_err(phy_common->dev, "%s: ufs_qcom_phy_init_clks() failed %d\n",
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__func__, err);
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goto out;
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}
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err = ufs_qcom_phy_init_vregulators(generic_phy, phy_common);
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if (err) {
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dev_err(phy_common->dev, "%s: ufs_qcom_phy_init_vregulators() failed %d\n",
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__func__, err);
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goto out;
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}
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ufs_qcom_phy_qmp_14nm_advertise_quirks(phy_common);
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if (phy_common->quirks & UFS_QCOM_PHY_QUIRK_VCO_MANUAL_TUNING) {
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phy_common->vco_tune1_mode1 = readl_relaxed(phy_common->mmio +
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QSERDES_COM_VCO_TUNE1_MODE1);
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dev_info(phy_common->dev, "%s: vco_tune1_mode1 0x%x\n",
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__func__, phy_common->vco_tune1_mode1);
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}
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out:
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return err;
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}
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static
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void ufs_qcom_phy_qmp_14nm_power_control(struct ufs_qcom_phy *phy,
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bool power_ctrl)
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{
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bool is_workaround_req = false;
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if (phy->quirks &
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UFS_QCOM_PHY_QUIRK_HIBERN8_EXIT_AFTER_PHY_PWR_COLLAPSE)
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is_workaround_req = true;
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if (!power_ctrl) {
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/* apply PHY analog power collapse */
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if (is_workaround_req) {
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/* assert common reset before analog power collapse */
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writel_relaxed(0x1, phy->mmio + QSERDES_COM_SW_RESET);
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/*
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* make sure that reset is propogated before analog
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* power collapse
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*/
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mb();
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}
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/* apply analog power collapse */
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writel_relaxed(0x0, phy->mmio + UFS_PHY_POWER_DOWN_CONTROL);
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/*
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* Make sure that PHY knows its analog rail is going to be
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* powered OFF.
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*/
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mb();
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} else {
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/* bring PHY out of analog power collapse */
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writel_relaxed(0x1, phy->mmio + UFS_PHY_POWER_DOWN_CONTROL);
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/*
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* Before any transactions involving PHY, ensure PHY knows
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* that it's analog rail is powered ON.
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*/
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mb();
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if (is_workaround_req) {
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/*
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* de-assert common reset after coming out of analog
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* power collapse
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*/
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writel_relaxed(0x0, phy->mmio + QSERDES_COM_SW_RESET);
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/* make common reset is de-asserted before proceeding */
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mb();
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}
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}
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}
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static inline
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void ufs_qcom_phy_qmp_14nm_set_tx_lane_enable(struct ufs_qcom_phy *phy, u32 val)
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{
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/*
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* 14nm PHY does not have TX_LANE_ENABLE register.
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* Implement this function so as not to propagate error to caller.
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*/
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}
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static
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void ufs_qcom_phy_qmp_14nm_ctrl_rx_linecfg(struct ufs_qcom_phy *phy, bool ctrl)
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{
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u32 temp;
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temp = readl_relaxed(phy->mmio + UFS_PHY_LINECFG_DISABLE);
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if (ctrl) /* enable RX LineCfg */
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temp &= ~UFS_PHY_RX_LINECFG_DISABLE_BIT;
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else /* disable RX LineCfg */
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temp |= UFS_PHY_RX_LINECFG_DISABLE_BIT;
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writel_relaxed(temp, phy->mmio + UFS_PHY_LINECFG_DISABLE);
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/* make sure that RX LineCfg config applied before we return */
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mb();
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}
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static inline void ufs_qcom_phy_qmp_14nm_start_serdes(struct ufs_qcom_phy *phy)
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{
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u32 tmp;
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tmp = readl_relaxed(phy->mmio + UFS_PHY_PHY_START);
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tmp &= ~MASK_SERDES_START;
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tmp |= (1 << OFFSET_SERDES_START);
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writel_relaxed(tmp, phy->mmio + UFS_PHY_PHY_START);
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/* Ensure register value is committed */
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mb();
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}
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static int ufs_qcom_phy_qmp_14nm_is_pcs_ready(struct ufs_qcom_phy *phy_common)
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{
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int err = 0;
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u32 val;
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err = readl_poll_timeout(phy_common->mmio + UFS_PHY_PCS_READY_STATUS,
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val, (val & MASK_PCS_READY), 10, 1000000);
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if (err) {
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dev_err(phy_common->dev, "%s: poll for pcs failed err = %d\n",
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__func__, err);
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goto out;
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}
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if (phy_common->quirks & UFS_QCOM_PHY_QUIRK_SVS_MODE) {
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int i;
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for (i = 0; i < ARRAY_SIZE(phy_svs_mode_config_2_0_0); i++)
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writel_relaxed(phy_svs_mode_config_2_0_0[i].cfg_value,
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(phy_common->mmio +
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phy_svs_mode_config_2_0_0[i].reg_offset));
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/* apply above configuration immediately */
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mb();
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}
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out:
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return err;
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}
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struct phy_ops ufs_qcom_phy_qmp_14nm_phy_ops = {
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.init = ufs_qcom_phy_qmp_14nm_init,
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.exit = ufs_qcom_phy_exit,
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.power_on = ufs_qcom_phy_power_on,
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.power_off = ufs_qcom_phy_power_off,
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.owner = THIS_MODULE,
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};
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struct ufs_qcom_phy_specific_ops phy_14nm_ops = {
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.calibrate_phy = ufs_qcom_phy_qmp_14nm_phy_calibrate,
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.start_serdes = ufs_qcom_phy_qmp_14nm_start_serdes,
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.is_physical_coding_sublayer_ready = ufs_qcom_phy_qmp_14nm_is_pcs_ready,
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.set_tx_lane_enable = ufs_qcom_phy_qmp_14nm_set_tx_lane_enable,
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.ctrl_rx_linecfg = ufs_qcom_phy_qmp_14nm_ctrl_rx_linecfg,
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.power_control = ufs_qcom_phy_qmp_14nm_power_control,
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};
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static int ufs_qcom_phy_qmp_14nm_probe(struct platform_device *pdev)
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{
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struct device *dev = &pdev->dev;
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struct phy *generic_phy;
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struct ufs_qcom_phy_qmp_14nm *phy;
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int err = 0;
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phy = devm_kzalloc(dev, sizeof(*phy), GFP_KERNEL);
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if (!phy) {
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dev_err(dev, "%s: failed to allocate phy\n", __func__);
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err = -ENOMEM;
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goto out;
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}
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generic_phy = ufs_qcom_phy_generic_probe(pdev, &phy->common_cfg,
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&ufs_qcom_phy_qmp_14nm_phy_ops, &phy_14nm_ops);
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if (!generic_phy) {
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dev_err(dev, "%s: ufs_qcom_phy_generic_probe() failed\n",
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__func__);
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err = -EIO;
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goto out;
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}
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phy_set_drvdata(generic_phy, phy);
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strlcpy(phy->common_cfg.name, UFS_PHY_NAME,
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sizeof(phy->common_cfg.name));
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out:
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return err;
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}
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static int ufs_qcom_phy_qmp_14nm_remove(struct platform_device *pdev)
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{
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struct device *dev = &pdev->dev;
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struct phy *generic_phy = to_phy(dev);
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struct ufs_qcom_phy *ufs_qcom_phy = get_ufs_qcom_phy(generic_phy);
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int err = 0;
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err = ufs_qcom_phy_remove(generic_phy, ufs_qcom_phy);
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if (err)
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dev_err(dev, "%s: ufs_qcom_phy_remove failed = %d\n",
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__func__, err);
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return err;
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}
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static const struct of_device_id ufs_qcom_phy_qmp_14nm_of_match[] = {
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{.compatible = "qcom,ufs-phy-qmp-14nm"},
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{},
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};
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MODULE_DEVICE_TABLE(of, ufs_qcom_phy_qmp_14nm_of_match);
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static struct platform_driver ufs_qcom_phy_qmp_14nm_driver = {
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.probe = ufs_qcom_phy_qmp_14nm_probe,
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.remove = ufs_qcom_phy_qmp_14nm_remove,
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.driver = {
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.of_match_table = ufs_qcom_phy_qmp_14nm_of_match,
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.name = "ufs_qcom_phy_qmp_14nm",
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.owner = THIS_MODULE,
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},
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};
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module_platform_driver(ufs_qcom_phy_qmp_14nm_driver);
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MODULE_DESCRIPTION("Universal Flash Storage (UFS) QCOM PHY QMP 14nm");
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MODULE_LICENSE("GPL v2");
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