2024-09-09 08:52:07 +00:00
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/*
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* Copyright (c) 2010 Broadcom Corporation
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
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* SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
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* OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
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* CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*/
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/*
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* phy_shim.h: stuff defined in phy_shim.c and included only by the phy
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*/
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#ifndef _BRCM_PHY_SHIM_H_
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#define _BRCM_PHY_SHIM_H_
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#include "types.h"
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#define RADAR_TYPE_NONE 0 /* Radar type None */
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#define RADAR_TYPE_ETSI_1 1 /* ETSI 1 Radar type */
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#define RADAR_TYPE_ETSI_2 2 /* ETSI 2 Radar type */
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#define RADAR_TYPE_ETSI_3 3 /* ETSI 3 Radar type */
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#define RADAR_TYPE_ITU_E 4 /* ITU E Radar type */
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#define RADAR_TYPE_ITU_K 5 /* ITU K Radar type */
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#define RADAR_TYPE_UNCLASSIFIED 6 /* Unclassified Radar type */
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#define RADAR_TYPE_BIN5 7 /* long pulse radar type */
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#define RADAR_TYPE_STG2 8 /* staggered-2 radar */
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#define RADAR_TYPE_STG3 9 /* staggered-3 radar */
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#define RADAR_TYPE_FRA 10 /* French radar */
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/* French radar pulse widths */
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#define FRA_T1_20MHZ 52770
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#define FRA_T2_20MHZ 61538
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#define FRA_T3_20MHZ 66002
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#define FRA_T1_40MHZ 105541
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#define FRA_T2_40MHZ 123077
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#define FRA_T3_40MHZ 132004
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#define FRA_ERR_20MHZ 60
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#define FRA_ERR_40MHZ 120
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#define ANTSEL_NA 0 /* No boardlevel selection available */
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#define ANTSEL_2x4 1 /* 2x4 boardlevel selection available */
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#define ANTSEL_2x3 2 /* 2x3 CB2 boardlevel selection available */
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/* Rx Antenna diversity control values */
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#define ANT_RX_DIV_FORCE_0 0 /* Use antenna 0 */
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#define ANT_RX_DIV_FORCE_1 1 /* Use antenna 1 */
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#define ANT_RX_DIV_START_1 2 /* Choose starting with 1 */
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#define ANT_RX_DIV_START_0 3 /* Choose starting with 0 */
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#define ANT_RX_DIV_ENABLE 3 /* APHY bbConfig Enable RX Diversity */
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#define ANT_RX_DIV_DEF ANT_RX_DIV_START_0 /* default antdiv setting */
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#define WL_ANT_RX_MAX 2 /* max 2 receive antennas */
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#define WL_ANT_HT_RX_MAX 3 /* max 3 receive antennas/cores */
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#define WL_ANT_IDX_1 0 /* antenna index 1 */
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#define WL_ANT_IDX_2 1 /* antenna index 2 */
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/* values for n_preamble_type */
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#define BRCMS_N_PREAMBLE_MIXEDMODE 0
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#define BRCMS_N_PREAMBLE_GF 1
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#define BRCMS_N_PREAMBLE_GF_BRCM 2
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#define WL_TX_POWER_RATES_LEGACY 45
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#define WL_TX_POWER_MCS20_FIRST 12
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#define WL_TX_POWER_MCS20_NUM 16
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#define WL_TX_POWER_MCS40_FIRST 28
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#define WL_TX_POWER_MCS40_NUM 17
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#define WL_TX_POWER_RATES 101
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#define WL_TX_POWER_CCK_FIRST 0
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#define WL_TX_POWER_CCK_NUM 4
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/* Index for first 20MHz OFDM SISO rate */
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#define WL_TX_POWER_OFDM_FIRST 4
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/* Index for first 20MHz OFDM CDD rate */
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#define WL_TX_POWER_OFDM20_CDD_FIRST 12
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/* Index for first 40MHz OFDM SISO rate */
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#define WL_TX_POWER_OFDM40_SISO_FIRST 52
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/* Index for first 40MHz OFDM CDD rate */
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#define WL_TX_POWER_OFDM40_CDD_FIRST 60
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#define WL_TX_POWER_OFDM_NUM 8
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/* Index for first 20MHz MCS SISO rate */
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#define WL_TX_POWER_MCS20_SISO_FIRST 20
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/* Index for first 20MHz MCS CDD rate */
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#define WL_TX_POWER_MCS20_CDD_FIRST 28
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/* Index for first 20MHz MCS STBC rate */
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#define WL_TX_POWER_MCS20_STBC_FIRST 36
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/* Index for first 20MHz MCS SDM rate */
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#define WL_TX_POWER_MCS20_SDM_FIRST 44
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/* Index for first 40MHz MCS SISO rate */
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#define WL_TX_POWER_MCS40_SISO_FIRST 68
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/* Index for first 40MHz MCS CDD rate */
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#define WL_TX_POWER_MCS40_CDD_FIRST 76
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/* Index for first 40MHz MCS STBC rate */
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#define WL_TX_POWER_MCS40_STBC_FIRST 84
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/* Index for first 40MHz MCS SDM rate */
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#define WL_TX_POWER_MCS40_SDM_FIRST 92
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#define WL_TX_POWER_MCS_1_STREAM_NUM 8
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#define WL_TX_POWER_MCS_2_STREAM_NUM 8
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/* Index for 40MHz rate MCS 32 */
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#define WL_TX_POWER_MCS_32 100
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#define WL_TX_POWER_MCS_32_NUM 1
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/* sslpnphy specifics */
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/* Index for first 20MHz MCS SISO rate */
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#define WL_TX_POWER_MCS20_SISO_FIRST_SSN 12
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/* struct tx_power::flags bits */
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#define WL_TX_POWER_F_ENABLED 1
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#define WL_TX_POWER_F_HW 2
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#define WL_TX_POWER_F_MIMO 4
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#define WL_TX_POWER_F_SISO 8
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/* values to force tx/rx chain */
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#define BRCMS_N_TXRX_CHAIN0 0
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#define BRCMS_N_TXRX_CHAIN1 1
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struct brcms_phy;
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2024-09-09 08:57:42 +00:00
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struct phy_shim_info *wlc_phy_shim_attach(struct brcms_hardware *wlc_hw,
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struct brcms_info *wl,
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struct brcms_c_info *wlc);
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void wlc_phy_shim_detach(struct phy_shim_info *physhim);
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2024-09-09 08:52:07 +00:00
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/* PHY to WL utility functions */
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2024-09-09 08:57:42 +00:00
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struct wlapi_timer *wlapi_init_timer(struct phy_shim_info *physhim,
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void (*fn)(struct brcms_phy *pi),
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void *arg, const char *name);
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void wlapi_free_timer(struct wlapi_timer *t);
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void wlapi_add_timer(struct wlapi_timer *t, uint ms, int periodic);
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bool wlapi_del_timer(struct wlapi_timer *t);
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void wlapi_intrson(struct phy_shim_info *physhim);
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u32 wlapi_intrsoff(struct phy_shim_info *physhim);
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void wlapi_intrsrestore(struct phy_shim_info *physhim, u32 macintmask);
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void wlapi_bmac_write_shm(struct phy_shim_info *physhim, uint offset, u16 v);
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u16 wlapi_bmac_read_shm(struct phy_shim_info *physhim, uint offset);
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void wlapi_bmac_mhf(struct phy_shim_info *physhim, u8 idx, u16 mask, u16 val,
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int bands);
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void wlapi_bmac_corereset(struct phy_shim_info *physhim, u32 flags);
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void wlapi_suspend_mac_and_wait(struct phy_shim_info *physhim);
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void wlapi_switch_macfreq(struct phy_shim_info *physhim, u8 spurmode);
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void wlapi_enable_mac(struct phy_shim_info *physhim);
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void wlapi_bmac_mctrl(struct phy_shim_info *physhim, u32 mask, u32 val);
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void wlapi_bmac_phy_reset(struct phy_shim_info *physhim);
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void wlapi_bmac_bw_set(struct phy_shim_info *physhim, u16 bw);
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void wlapi_bmac_phyclk_fgc(struct phy_shim_info *physhim, bool clk);
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void wlapi_bmac_macphyclk_set(struct phy_shim_info *physhim, bool clk);
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void wlapi_bmac_core_phypll_ctl(struct phy_shim_info *physhim, bool on);
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void wlapi_bmac_core_phypll_reset(struct phy_shim_info *physhim);
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void wlapi_bmac_ucode_wake_override_phyreg_set(struct phy_shim_info *physhim);
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void wlapi_bmac_ucode_wake_override_phyreg_clear(struct phy_shim_info *physhim);
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void wlapi_bmac_write_template_ram(struct phy_shim_info *physhim, int o,
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int len, void *buf);
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u16 wlapi_bmac_rate_shm_offset(struct phy_shim_info *physhim, u8 rate);
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void wlapi_ucode_sample_init(struct phy_shim_info *physhim);
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void wlapi_copyfrom_objmem(struct phy_shim_info *physhim, uint, void *buf,
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int, u32 sel);
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void wlapi_copyto_objmem(struct phy_shim_info *physhim, uint, const void *buf,
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int, u32);
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void wlapi_high_update_phy_mode(struct phy_shim_info *physhim, u32 phy_mode);
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u16 wlapi_bmac_get_txant(struct phy_shim_info *physhim);
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2024-09-09 08:52:07 +00:00
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#endif /* _BRCM_PHY_SHIM_H_ */
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