239 lines
8.2 KiB
C
239 lines
8.2 KiB
C
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/* Copyright (c) 2015-2016, The Linux Foundation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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* only version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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/* Qualcomm Technologies, Inc. EMAC SGMII Controller driver.
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*/
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#include "emac_sgmii.h"
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#include "emac_hw.h"
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#define PCS_MAX_REG_CNT 10
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#define PLL_MAX_REG_CNT 18
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static const struct emac_reg_write
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physical_coding_sublayer_programming[][PCS_MAX_REG_CNT] = {
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/* EMAC_PHY_MAP_DEFAULT */
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{
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{EMAC_SGMII_PHY_CDR_CTRL0, SGMII_CDR_MAX_CNT},
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{EMAC_SGMII_PHY_POW_DWN_CTRL0, PWRDN_B},
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{EMAC_SGMII_PHY_CMN_PWR_CTRL, BIAS_EN | SYSCLK_EN |
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CLKBUF_L_EN | PLL_TXCLK_EN | PLL_RXCLK_EN},
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{EMAC_SGMII_PHY_TX_PWR_CTRL, L0_TX_EN | L0_CLKBUF_EN |
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L0_TRAN_BIAS_EN},
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{EMAC_SGMII_PHY_RX_PWR_CTRL, L0_RX_SIGDET_EN |
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(1 << L0_RX_TERM_MODE_SHFT) | L0_RX_I_EN},
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{EMAC_SGMII_PHY_CMN_PWR_CTRL, BIAS_EN | PLL_EN | SYSCLK_EN |
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CLKBUF_L_EN | PLL_TXCLK_EN | PLL_RXCLK_EN},
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{EMAC_SGMII_PHY_LANE_CTRL1, L0_RX_EQ_EN |
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L0_RESET_TSYNC_EN | L0_DRV_LVL_BMSK},
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{END_MARKER, END_MARKER},
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},
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/* EMAC_PHY_MAP_MDM9607 */
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{
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{EMAC_SGMII_PHY_CDR_CTRL0, SGMII_CDR_MAX_CNT},
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{EMAC_SGMII_PHY_POW_DWN_CTRL0, PWRDN_B},
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{EMAC_SGMII_PHY_CMN_PWR_CTRL, BIAS_EN | SYSCLK_EN |
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CLKBUF_L_EN | PLL_TXCLK_EN | PLL_RXCLK_EN},
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{EMAC_SGMII_PHY_TX_PWR_CTRL, L0_TX_EN | L0_CLKBUF_EN |
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L0_TRAN_BIAS_EN},
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{EMAC_SGMII_PHY_RX_PWR_CTRL, L0_RX_SIGDET_EN |
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(1 << L0_RX_TERM_MODE_SHFT) | L0_RX_I_EN},
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{EMAC_SGMII_PHY_CMN_PWR_CTRL, BIAS_EN | PLL_EN | SYSCLK_EN |
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CLKBUF_L_EN | PLL_TXCLK_EN | PLL_RXCLK_EN},
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{EMAC_QSERDES_COM_PLL_VCOTAIL_EN, PLL_VCO_TAIL_MUX |
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PLL_VCO_TAIL | PLL_EN_VCOTAIL_EN},
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{EMAC_QSERDES_COM_PLL_CNTRL, OCP_EN | PLL_DIV_FFEN |
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PLL_DIV_ORD},
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{EMAC_SGMII_PHY_LANE_CTRL1, L0_RX_EQ_EN |
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L0_RESET_TSYNC_EN | L0_DRV_LVL_BMSK},
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{END_MARKER, END_MARKER}
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}
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};
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static const struct emac_reg_write sysclk_refclk_setting[] = {
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{EMAC_QSERDES_COM_SYSCLK_EN_SEL, SYSCLK_SEL_CMOS},
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{EMAC_QSERDES_COM_SYS_CLK_CTRL, SYSCLK_CM | SYSCLK_AC_COUPLE},
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{END_MARKER, END_MARKER},
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};
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static const struct emac_reg_write pll_setting[][PLL_MAX_REG_CNT] = {
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/* EMAC_PHY_MAP_DEFAULT */
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{
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{EMAC_QSERDES_COM_PLL_IP_SETI, QSERDES_PLL_IPSETI_DEF},
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{EMAC_QSERDES_COM_PLL_CP_SETI, QSERDES_PLL_CP_SETI},
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{EMAC_QSERDES_COM_PLL_IP_SETP, QSERDES_PLL_IP_SETP},
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{EMAC_QSERDES_COM_PLL_CP_SETP, QSERDES_PLL_CP_SETP},
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{EMAC_QSERDES_COM_PLL_CRCTRL, QSERDES_PLL_CRCTRL},
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{EMAC_QSERDES_COM_PLL_CNTRL, OCP_EN | PLL_DIV_FFEN |
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PLL_DIV_ORD},
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{EMAC_QSERDES_COM_DEC_START1, DEC_START1_MUX |
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QSERDES_PLL_DEC},
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{EMAC_QSERDES_COM_DEC_START2, DEC_START2_MUX |
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DEC_START2},
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{EMAC_QSERDES_COM_DIV_FRAC_START1, DIV_FRAC_START1_MUX |
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QSERDES_PLL_DIV_FRAC_START1},
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{EMAC_QSERDES_COM_DIV_FRAC_START2, DIV_FRAC_START2_MUX |
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QSERDES_PLL_DIV_FRAC_START2},
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{EMAC_QSERDES_COM_DIV_FRAC_START3, DIV_FRAC_START3_MUX |
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QSERDES_PLL_DIV_FRAC_START3},
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{EMAC_QSERDES_COM_PLLLOCK_CMP1, QSERDES_PLL_LOCK_CMP1},
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{EMAC_QSERDES_COM_PLLLOCK_CMP2, QSERDES_PLL_LOCK_CMP2},
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{EMAC_QSERDES_COM_PLLLOCK_CMP3, QSERDES_PLL_LOCK_CMP3},
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{EMAC_QSERDES_COM_PLLLOCK_CMP_EN, PLLLOCK_CMP_EN},
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{EMAC_QSERDES_COM_RESETSM_CNTRL, FRQ_TUNE_MODE},
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{END_MARKER, END_MARKER}
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},
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/* EMAC_PHY_MAP_MDM9607 */
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{
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{EMAC_QSERDES_COM_PLL_IP_SETI, QSERDES_PLL_IPSETI_MDM},
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{EMAC_QSERDES_COM_PLL_CP_SETI, QSERDES_PLL_CP_SETI},
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{EMAC_QSERDES_COM_PLL_IP_SETP, QSERDES_PLL_IP_SETP},
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{EMAC_QSERDES_COM_PLL_CP_SETP, QSERDES_PLL_CP_SETP},
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{EMAC_QSERDES_COM_PLL_CRCTRL, QSERDES_PLL_CRCTRL},
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{EMAC_QSERDES_COM_DEC_START1, DEC_START1_MUX |
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QSERDES_PLL_DEC},
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{EMAC_QSERDES_COM_DEC_START2, DEC_START2_MUX |
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DEC_START2},
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{EMAC_QSERDES_COM_DIV_FRAC_START1, DIV_FRAC_START1_MUX |
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QSERDES_PLL_DIV_FRAC_START1},
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{EMAC_QSERDES_COM_DIV_FRAC_START2, DIV_FRAC_START2_MUX |
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QSERDES_PLL_DIV_FRAC_START2},
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{EMAC_QSERDES_COM_DIV_FRAC_START3, DIV_FRAC_START3_MUX |
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QSERDES_PLL_DIV_FRAC_START3},
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{EMAC_QSERDES_COM_PLLLOCK_CMP1, QSERDES_PLL_LOCK_CMP1},
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{EMAC_QSERDES_COM_PLLLOCK_CMP2, QSERDES_PLL_LOCK_CMP2},
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{EMAC_QSERDES_COM_PLLLOCK_CMP3, QSERDES_PLL_LOCK_CMP3},
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{EMAC_QSERDES_COM_PLLLOCK_CMP_EN, PLLLOCK_CMP_EN},
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{EMAC_QSERDES_COM_RESETSM_CNTRL, FRQ_TUNE_MODE},
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{EMAC_QSERDES_COM_RES_TRIM_SEARCH, RESTRIM_SEARCH},
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{EMAC_QSERDES_COM_BGTC, BGTC},
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{END_MARKER, END_MARKER},
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}
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};
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static const struct emac_reg_write cdr_setting[] = {
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{EMAC_QSERDES_RX_CDR_CONTROL, SECONDORDERENABLE |
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(QSERDES_RX_CDR_CTRL1_THRESH << FIRSTORDER_THRESH_SHFT) |
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(QSERDES_RX_CDR_CTRL1_GAIN << SECONDORDERGAIN_SHFT)},
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{EMAC_QSERDES_RX_CDR_CONTROL2, SECONDORDERENABLE |
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(QSERDES_RX_CDR_CTRL2_THRESH << FIRSTORDER_THRESH_SHFT) |
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(QSERDES_RX_CDR_CTRL2_GAIN << SECONDORDERGAIN_SHFT)},
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{END_MARKER, END_MARKER},
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};
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static const struct emac_reg_write tx_rx_setting[] = {
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{EMAC_QSERDES_TX_BIST_MODE_LANENO, QSERDES_TX_BIST_MODE_LANENO},
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{EMAC_QSERDES_TX_TX_DRV_LVL, TX_DRV_LVL_MUX |
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(QSERDES_TX_DRV_LVL << TX_DRV_LVL_SHFT)},
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{EMAC_QSERDES_TX_TRAN_DRVR_EMP_EN, EMP_EN_MUX | EMP_EN},
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{EMAC_QSERDES_TX_TX_EMP_POST1_LVL, TX_EMP_POST1_LVL_MUX |
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(QSERDES_TX_EMP_POST1_LVL << TX_EMP_POST1_LVL_SHFT)},
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{EMAC_QSERDES_RX_RX_EQ_GAIN12,
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(QSERDES_RX_EQ_GAIN2 << RX_EQ_GAIN2_SHFT) |
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(QSERDES_RX_EQ_GAIN1 << RX_EQ_GAIN1_SHFT)},
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{EMAC_QSERDES_TX_LANE_MODE,
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QSERDES_TX_LANE_MODE},
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{END_MARKER, END_MARKER}
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};
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static int emac_sgmii_v1_init(struct emac_adapter *adpt)
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{
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int i;
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struct emac_phy *phy = &adpt->phy;
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struct emac_sgmii *sgmii = phy->private;
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emac_sgmii_init_link(adpt, phy->autoneg_advertised, phy->autoneg,
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!phy->disable_fc_autoneg);
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emac_reg_write_all(
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sgmii->base,
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(const struct emac_reg_write *)
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&physical_coding_sublayer_programming[phy->board_id]);
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/* Ensure Rx/Tx lanes power configuration is written to hw before
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* configuring the SerDes engine's clocks
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*/
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wmb();
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emac_reg_write_all(sgmii->base, sysclk_refclk_setting);
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emac_reg_write_all(
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sgmii->base,
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(const struct emac_reg_write *)&pll_setting[phy->board_id]);
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emac_reg_write_all(sgmii->base, cdr_setting);
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emac_reg_write_all(sgmii->base, tx_rx_setting);
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/* Ensure SerDes engine configuration is written to hw before powering
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* it up
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*/
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wmb();
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writel_relaxed(SERDES_START, sgmii->base + EMAC_SGMII_PHY_SERDES_START);
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/* Ensure Rx/Tx SerDes engine power-up command is written to HW */
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wmb();
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for (i = 0; i < SERDES_START_WAIT_TIMES; i++) {
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if (readl_relaxed(sgmii->base + EMAC_QSERDES_COM_RESET_SM) &
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QSERDES_READY)
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break;
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usleep_range(100, 200);
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}
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if (i == SERDES_START_WAIT_TIMES) {
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emac_err(adpt, "serdes failed to start\n");
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return -EIO;
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}
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/* Mask out all the SGMII Interrupt */
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writel_relaxed(0, sgmii->base + EMAC_SGMII_PHY_INTERRUPT_MASK);
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/* Ensure SGMII interrupts are masked out before clearing them */
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wmb();
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emac_hw_clear_sgmii_intr_status(adpt, SGMII_PHY_INTERRUPT_ERR);
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return 0;
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}
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static void emac_sgmii_v1_reset(struct emac_adapter *adpt)
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{
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emac_clk_set_rate(adpt, EMAC_CLK_125M, EMC_CLK_RATE_19_2MHZ);
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emac_sgmii_reset_prepare(adpt);
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emac_sgmii_v1_init(adpt);
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emac_clk_set_rate(adpt, EMAC_CLK_125M, EMC_CLK_RATE_125MHZ);
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}
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int emac_sgmii_v1_link_setup_no_ephy(struct emac_adapter *adpt, u32 speed,
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bool autoneg)
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{
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struct emac_phy *phy = &adpt->phy;
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phy->autoneg = autoneg;
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phy->autoneg_advertised = speed;
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/* The AN_ENABLE and SPEED_CFG can't change on fly. The SGMII_PHY has
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* to be re-initialized.
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*/
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emac_sgmii_reset_prepare(adpt);
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return emac_sgmii_v1_init(adpt);
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}
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struct emac_phy_ops emac_sgmii_v1_ops = {
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.config = emac_sgmii_config,
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.up = emac_sgmii_up,
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.down = emac_sgmii_down,
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.init = emac_sgmii_v1_init,
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.reset = emac_sgmii_v1_reset,
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.init_ephy = emac_sgmii_init_ephy_nop,
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.link_setup_no_ephy = emac_sgmii_v1_link_setup_no_ephy,
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.link_check_no_ephy = emac_sgmii_link_check_no_ephy,
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.tx_clk_set_rate = emac_sgmii_tx_clk_set_rate_nop,
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.periodic_task = emac_sgmii_periodic_check,
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};
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