333 lines
8.2 KiB
C
333 lines
8.2 KiB
C
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/* Copyright (c) 2015, The Linux Foundation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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* only version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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/* Qualcomm Technologies, Inc. EMAC SGMII Controller driver.
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*/
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#include "emac_sgmii.h"
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#include "emac_hw.h"
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int emac_sgmii_config(struct platform_device *pdev, struct emac_adapter *adpt)
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{
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struct emac_sgmii *sgmii;
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struct resource *res;
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int ret;
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sgmii = devm_kzalloc(&pdev->dev, sizeof(*sgmii), GFP_KERNEL);
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if (!sgmii)
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return -ENOMEM;
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ret = platform_get_irq_byname(pdev, "emac_sgmii_irq");
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if (ret < 0)
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return ret;
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sgmii->irq = ret;
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res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "emac_sgmii");
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if (!res) {
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emac_err(adpt,
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"error platform_get_resource_byname(emac_sgmii)\n");
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return -ENOENT;
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}
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sgmii->base = devm_ioremap_resource(&pdev->dev, res);
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if (IS_ERR(sgmii->base)) {
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emac_err(adpt,
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"error:%ld devm_ioremap_resource(start:0x%lx size:0x%lx)\n",
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PTR_ERR(sgmii->base), (ulong)res->start,
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(ulong)resource_size(res));
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return -ENOMEM;
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}
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adpt->phy.private = sgmii;
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return 0;
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}
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void emac_sgmii_reset_prepare(struct emac_adapter *adpt)
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{
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struct emac_sgmii *sgmii = adpt->phy.private;
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u32 val;
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val = readl_relaxed(sgmii->base + EMAC_EMAC_WRAPPER_CSR2);
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writel_relaxed(((val & ~PHY_RESET) | PHY_RESET),
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sgmii->base + EMAC_EMAC_WRAPPER_CSR2);
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/* Ensure phy-reset command is written to HW before the release cmd */
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wmb();
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msleep(50);
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val = readl_relaxed(sgmii->base + EMAC_EMAC_WRAPPER_CSR2);
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writel_relaxed((val & ~PHY_RESET),
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sgmii->base + EMAC_EMAC_WRAPPER_CSR2);
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/* Ensure phy-reset release command is written to HW before initializing
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* SGMII
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*/
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wmb();
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msleep(50);
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}
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/* LINK */
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int emac_sgmii_init_link(struct emac_adapter *adpt, u32 speed, bool autoneg,
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bool fc)
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{
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struct emac_sgmii *sgmii = adpt->phy.private;
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u32 val;
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u32 speed_cfg = 0;
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val = readl_relaxed(sgmii->base + EMAC_SGMII_PHY_AUTONEG_CFG2);
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if (autoneg) {
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val &= ~(FORCE_AN_RX_CFG | FORCE_AN_TX_CFG);
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val |= AN_ENABLE;
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writel_relaxed(val, sgmii->base + EMAC_SGMII_PHY_AUTONEG_CFG2);
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} else {
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switch (speed) {
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case EMAC_LINK_SPEED_10_HALF:
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speed_cfg = SPDMODE_10;
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break;
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case EMAC_LINK_SPEED_10_FULL:
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speed_cfg = SPDMODE_10 | DUPLEX_MODE;
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break;
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case EMAC_LINK_SPEED_100_HALF:
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speed_cfg = SPDMODE_100;
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break;
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case EMAC_LINK_SPEED_100_FULL:
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speed_cfg = SPDMODE_100 | DUPLEX_MODE;
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break;
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case EMAC_LINK_SPEED_1GB_FULL:
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speed_cfg = SPDMODE_1000 | DUPLEX_MODE;
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break;
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default:
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return -EINVAL;
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}
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val &= ~AN_ENABLE;
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writel_relaxed(speed_cfg,
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sgmii->base + EMAC_SGMII_PHY_SPEED_CFG1);
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writel_relaxed(val, sgmii->base + EMAC_SGMII_PHY_AUTONEG_CFG2);
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}
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/* Ensure Auto-Neg setting are written to HW before leaving */
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wmb();
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return 0;
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}
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int emac_hw_clear_sgmii_intr_status(struct emac_adapter *adpt, u32 irq_bits)
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{
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struct emac_sgmii *sgmii = adpt->phy.private;
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u32 status;
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int i;
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writel_relaxed(irq_bits, sgmii->base + EMAC_SGMII_PHY_INTERRUPT_CLEAR);
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writel_relaxed(IRQ_GLOBAL_CLEAR, sgmii->base + EMAC_SGMII_PHY_IRQ_CMD);
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/* Ensure interrupt clear command is written to HW */
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wmb();
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/* After set the IRQ_GLOBAL_CLEAR bit, the status clearing must
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* be confirmed before clearing the bits in other registers.
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* It takes a few cycles for hw to clear the interrupt status.
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*/
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for (i = 0; i < SGMII_PHY_IRQ_CLR_WAIT_TIME; i++) {
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udelay(1);
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status = readl_relaxed(sgmii->base +
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EMAC_SGMII_PHY_INTERRUPT_STATUS);
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if (!(status & irq_bits))
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break;
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}
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if (status & irq_bits) {
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emac_err(adpt,
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"failed to clear SGMII irq: status 0x%x bits 0x%x\n",
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status, irq_bits);
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return -EIO;
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}
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/* Finalize clearing procedure */
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writel_relaxed(0, sgmii->base + EMAC_SGMII_PHY_IRQ_CMD);
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writel_relaxed(0, sgmii->base + EMAC_SGMII_PHY_INTERRUPT_CLEAR);
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/* Ensure that clearing procedure finalization is written to HW */
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wmb();
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return 0;
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}
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int emac_sgmii_init_ephy_nop(struct emac_adapter *adpt)
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{
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return 0;
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}
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int emac_sgmii_autoneg_check(struct emac_adapter *adpt, u32 *speed,
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bool *link_up)
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{
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struct emac_sgmii *sgmii = adpt->phy.private;
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u32 autoneg0, autoneg1, status;
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autoneg0 = readl_relaxed(sgmii->base + EMAC_SGMII_PHY_AUTONEG0_STATUS);
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autoneg1 = readl_relaxed(sgmii->base + EMAC_SGMII_PHY_AUTONEG1_STATUS);
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status = ((autoneg1 & 0xff) << 8) | (autoneg0 & 0xff);
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if (!(status & TXCFG_LINK)) {
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*link_up = false;
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*speed = EMAC_LINK_SPEED_UNKNOWN;
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return 0;
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}
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*link_up = true;
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switch (status & TXCFG_MODE_BMSK) {
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case TXCFG_1000_FULL:
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*speed = EMAC_LINK_SPEED_1GB_FULL;
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break;
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case TXCFG_100_FULL:
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*speed = EMAC_LINK_SPEED_100_FULL;
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break;
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case TXCFG_100_HALF:
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*speed = EMAC_LINK_SPEED_100_HALF;
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break;
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case TXCFG_10_FULL:
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*speed = EMAC_LINK_SPEED_10_FULL;
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break;
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case TXCFG_10_HALF:
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*speed = EMAC_LINK_SPEED_10_HALF;
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break;
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default:
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*speed = EMAC_LINK_SPEED_UNKNOWN;
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break;
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}
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return 0;
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}
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int emac_sgmii_link_check_no_ephy(struct emac_adapter *adpt, u32 *speed,
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bool *link_up)
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{
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struct emac_sgmii *sgmii = adpt->phy.private;
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u32 val;
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val = readl_relaxed(sgmii->base + EMAC_SGMII_PHY_AUTONEG_CFG2);
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if (val & AN_ENABLE)
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return emac_sgmii_autoneg_check(adpt, speed, link_up);
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val = readl_relaxed(sgmii->base + EMAC_SGMII_PHY_SPEED_CFG1);
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val &= DUPLEX_MODE | SPDMODE_BMSK;
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switch (val) {
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case DUPLEX_MODE | SPDMODE_1000:
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*speed = EMAC_LINK_SPEED_1GB_FULL;
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break;
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case DUPLEX_MODE | SPDMODE_100:
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*speed = EMAC_LINK_SPEED_100_FULL;
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break;
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case SPDMODE_100:
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*speed = EMAC_LINK_SPEED_100_HALF;
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break;
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case DUPLEX_MODE | SPDMODE_10:
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*speed = EMAC_LINK_SPEED_10_FULL;
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break;
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case SPDMODE_10:
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*speed = EMAC_LINK_SPEED_10_HALF;
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break;
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default:
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*speed = EMAC_LINK_SPEED_UNKNOWN;
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break;
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}
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*link_up = true;
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return 0;
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}
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irqreturn_t emac_sgmii_isr(int _irq, void *data)
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{
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struct emac_adapter *adpt = data;
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struct emac_sgmii *sgmii = adpt->phy.private;
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u32 status;
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emac_dbg(adpt, intr, "receive sgmii interrupt\n");
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do {
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status = readl_relaxed(sgmii->base +
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EMAC_SGMII_PHY_INTERRUPT_STATUS) &
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SGMII_ISR_MASK;
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if (!status)
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break;
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if (status & SGMII_PHY_INTERRUPT_ERR) {
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SET_FLAG(adpt, ADPT_TASK_CHK_SGMII_REQ);
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if (!TEST_FLAG(adpt, ADPT_STATE_DOWN))
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emac_task_schedule(adpt);
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}
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if (status & SGMII_ISR_AN_MASK)
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emac_check_lsc(adpt);
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if (emac_hw_clear_sgmii_intr_status(adpt, status) != 0) {
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/* reset */
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SET_FLAG(adpt, ADPT_TASK_REINIT_REQ);
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emac_task_schedule(adpt);
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break;
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}
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} while (1);
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return IRQ_HANDLED;
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}
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int emac_sgmii_up(struct emac_adapter *adpt)
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{
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struct emac_sgmii *sgmii = adpt->phy.private;
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int ret;
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ret = request_irq(sgmii->irq, emac_sgmii_isr, IRQF_TRIGGER_RISING,
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"sgmii_irq", adpt);
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if (ret)
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emac_err(adpt,
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"error:%d on request_irq(%d:sgmii_irq)\n", ret,
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sgmii->irq);
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/* enable sgmii irq */
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writel_relaxed(SGMII_ISR_MASK,
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sgmii->base + EMAC_SGMII_PHY_INTERRUPT_MASK);
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return ret;
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}
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void emac_sgmii_down(struct emac_adapter *adpt)
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{
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struct emac_sgmii *sgmii = adpt->phy.private;
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writel_relaxed(0, sgmii->base + EMAC_SGMII_PHY_INTERRUPT_MASK);
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synchronize_irq(sgmii->irq);
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free_irq(sgmii->irq, adpt);
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}
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void emac_sgmii_tx_clk_set_rate_nop(struct emac_adapter *adpt)
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{
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}
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/* Check SGMII for error */
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void emac_sgmii_periodic_check(struct emac_adapter *adpt)
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{
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struct emac_sgmii *sgmii = adpt->phy.private;
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if (!TEST_FLAG(adpt, ADPT_TASK_CHK_SGMII_REQ))
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return;
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CLR_FLAG(adpt, ADPT_TASK_CHK_SGMII_REQ);
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/* ensure that no reset is in progress while link task is running */
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while (TEST_N_SET_FLAG(adpt, ADPT_STATE_RESETTING))
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msleep(20); /* Reset might take few 10s of ms */
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if (TEST_FLAG(adpt, ADPT_STATE_DOWN))
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goto sgmii_task_done;
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if (readl_relaxed(sgmii->base + EMAC_SGMII_PHY_RX_CHK_STATUS) & 0x40)
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goto sgmii_task_done;
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emac_err(adpt, "SGMII CDR not locked\n");
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sgmii_task_done:
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CLR_FLAG(adpt, ADPT_STATE_RESETTING);
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}
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