153 lines
4.6 KiB
C
153 lines
4.6 KiB
C
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/* Copyright (c) 2013-2016, The Linux Foundation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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* only version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef _EMAC_HW_H_
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#define _EMAC_HW_H_
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#include <linux/mii.h>
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#include "emac.h"
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#include "emac_regs.h"
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#include "emac_defines.h"
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/* function prototype */
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/* REG */
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u32 emac_reg_r32(struct emac_hw *hw, u8 base, u32 reg);
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void emac_reg_w32(struct emac_hw *hw, u8 base, u32 reg, u32 val);
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void emac_reg_update32(struct emac_hw *hw, u8 base, u32 reg,
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u32 mask, u32 val);
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u32 emac_reg_field_r32(struct emac_hw *hw, u8 base, u32 reg,
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u32 mask, u32 shift);
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void emac_hw_config_pow_save(struct emac_hw *hw, u32 speed, bool wol_en,
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bool rx_en);
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/* MAC */
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void emac_hw_enable_intr(struct emac_hw *hw);
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void emac_hw_disable_intr(struct emac_hw *hw);
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void emac_hw_set_mc_addr(struct emac_hw *hw, u8 *addr);
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void emac_hw_clear_mc_addr(struct emac_hw *hw);
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void emac_hw_config_mac_ctrl(struct emac_hw *hw);
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void emac_hw_config_rss(struct emac_hw *hw);
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void emac_hw_config_wol(struct emac_hw *hw, u32 wufc);
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int emac_hw_config_fc(struct emac_hw *hw);
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void emac_hw_reset_mac(struct emac_hw *hw);
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void emac_hw_config_mac(struct emac_hw *hw);
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void emac_hw_start_mac(struct emac_hw *hw);
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void emac_hw_stop_mac(struct emac_hw *hw);
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void emac_hw_set_mac_addr(struct emac_hw *hw, u8 *addr);
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/* TX Timestamp */
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bool emac_hw_read_tx_tstamp(struct emac_hw *hw, struct emac_hwtxtstamp *ts);
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#define IMR_NORMAL_MASK (\
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ISR_ERROR |\
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ISR_GPHY_LINK |\
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ISR_TX_PKT |\
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GPHY_WAKEUP_INT)
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#define IMR_EXTENDED_MASK (\
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SW_MAN_INT |\
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ISR_OVER |\
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ISR_ERROR |\
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ISR_GPHY_LINK |\
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ISR_TX_PKT |\
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GPHY_WAKEUP_INT)
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#define ISR_RX_PKT (\
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RX_PKT_INT0 |\
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RX_PKT_INT1 |\
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RX_PKT_INT2 |\
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RX_PKT_INT3)
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#define ISR_TX_PKT (\
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TX_PKT_INT |\
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TX_PKT_INT1 |\
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TX_PKT_INT2 |\
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TX_PKT_INT3)
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#define ISR_GPHY_LINK (\
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GPHY_LINK_UP_INT |\
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GPHY_LINK_DOWN_INT)
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#define ISR_OVER (\
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RFD0_UR_INT |\
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RFD1_UR_INT |\
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RFD2_UR_INT |\
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RFD3_UR_INT |\
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RFD4_UR_INT |\
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RXF_OF_INT |\
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TXF_UR_INT)
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#define ISR_ERROR (\
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DMAR_TO_INT |\
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DMAW_TO_INT |\
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TXQ_TO_INT)
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#define REG_MAC_RX_STATUS_BIN EMAC_RXMAC_STATC_REG0
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#define REG_MAC_RX_STATUS_END EMAC_RXMAC_STATC_REG22
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#define REG_MAC_TX_STATUS_BIN EMAC_TXMAC_STATC_REG0
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#define REG_MAC_TX_STATUS_END EMAC_TXMAC_STATC_REG24
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#define RXQ0_NUM_RFD_PREF_DEF 8
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#define TXQ0_NUM_TPD_PREF_DEF 5
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#define EMAC_PREAMBLE_DEF 7
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#define DMAR_DLY_CNT_DEF 15
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#define DMAW_DLY_CNT_DEF 4
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#define MDIO_CLK_25_4 0
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#define MDIO_CLK_25_28 7
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#define RXQ0_RSS_HSTYP_IPV6_TCP_EN 0x20
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#define RXQ0_RSS_HSTYP_IPV6_EN 0x10
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#define RXQ0_RSS_HSTYP_IPV4_TCP_EN 0x8
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#define RXQ0_RSS_HSTYP_IPV4_EN 0x4
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#define MASTER_CTRL_CLK_SEL_DIS 0x1000
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#define MDIO_WAIT_TIMES 1000
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/* PHY */
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#define MII_PSSR 0x11 /* PHY Specific Status Reg */
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#define MII_DBG_ADDR 0x1D /* PHY Debug Address Reg */
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#define MII_DBG_DATA 0x1E /* PHY Debug Data Reg */
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#define MII_INT_ENABLE 0x12 /* PHY Interrupt Enable Reg */
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#define MII_INT_STATUS 0x13 /* PHY Interrupt Status Reg */
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/* MII_BMCR (0x00) */
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#define BMCR_SPEED10 0x0000
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/* MII_PSSR (0x11) */
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#define PSSR_FC_RXEN 0x0004
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#define PSSR_FC_TXEN 0x0008
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#define PSSR_SPD_DPLX_RESOLVED 0x0800 /* 1=Speed & Duplex resolved */
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#define PSSR_DPLX 0x2000 /* 1=Duplex 0=Half Duplex */
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#define PSSR_SPEED 0xC000 /* Speed, bits 14:15 */
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#define PSSR_10MBS 0x0000 /* 00=10Mbs */
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#define PSSR_100MBS 0x4000 /* 01=100Mbs */
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#define PSSR_1000MBS 0x8000 /* 10=1000Mbs */
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/* MII DBG registers */
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#define HIBERNATE_CTRL_REG 0xB
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/* HIBERNATE_CTRL_REG */
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#define HIBERNATE_EN 0x8000
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/* MII_INT_ENABLE/MII_INT_STATUS */
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#define LINK_SUCCESS_INTERRUPT 0x400
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#define LINK_SUCCESS_BX 0x80
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#endif /*_EMAC_HW_H_*/
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