2024-09-09 08:52:07 +00:00
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/*
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* Copyright (c) 2004, 2005 Topspin Communications. All rights reserved.
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* Copyright (c) 2005 Mellanox Technologies. All rights reserved.
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* Copyright (c) 2006, 2007 Cisco Systems, Inc. All rights reserved.
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*
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* This software is available to you under a choice of one of two
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* licenses. You may choose to be licensed under the terms of the GNU
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* General Public License (GPL) Version 2, available from the file
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* COPYING in the main directory of this source tree, or the
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* OpenIB.org BSD license below:
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*
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* Redistribution and use in source and binary forms, with or
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* without modification, are permitted provided that the following
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* conditions are met:
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*
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* - Redistributions of source code must retain the above
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* copyright notice, this list of conditions and the following
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* disclaimer.
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*
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* - Redistributions in binary form must reproduce the above
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* copyright notice, this list of conditions and the following
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* disclaimer in the documentation and/or other materials
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* provided with the distribution.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
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* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*/
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#include <linux/slab.h>
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#include "mlx4.h"
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#include "fw.h"
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enum {
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MLX4_RES_QP,
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MLX4_RES_RDMARC,
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MLX4_RES_ALTC,
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MLX4_RES_AUXC,
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MLX4_RES_SRQ,
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MLX4_RES_CQ,
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MLX4_RES_EQ,
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MLX4_RES_DMPT,
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MLX4_RES_CMPT,
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MLX4_RES_MTT,
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MLX4_RES_MCG,
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MLX4_RES_NUM
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};
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static const char *res_name[] = {
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[MLX4_RES_QP] = "QP",
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[MLX4_RES_RDMARC] = "RDMARC",
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[MLX4_RES_ALTC] = "ALTC",
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[MLX4_RES_AUXC] = "AUXC",
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[MLX4_RES_SRQ] = "SRQ",
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[MLX4_RES_CQ] = "CQ",
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[MLX4_RES_EQ] = "EQ",
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[MLX4_RES_DMPT] = "DMPT",
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[MLX4_RES_CMPT] = "CMPT",
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[MLX4_RES_MTT] = "MTT",
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[MLX4_RES_MCG] = "MCG",
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};
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u64 mlx4_make_profile(struct mlx4_dev *dev,
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struct mlx4_profile *request,
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struct mlx4_dev_cap *dev_cap,
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struct mlx4_init_hca_param *init_hca)
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{
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struct mlx4_priv *priv = mlx4_priv(dev);
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struct mlx4_resource {
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u64 size;
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u64 start;
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int type;
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2024-09-09 08:57:42 +00:00
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u32 num;
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2024-09-09 08:52:07 +00:00
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int log_num;
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};
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u64 total_size = 0;
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struct mlx4_resource *profile;
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struct mlx4_resource tmp;
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struct sysinfo si;
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int i, j;
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profile = kcalloc(MLX4_RES_NUM, sizeof(*profile), GFP_KERNEL);
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if (!profile)
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return -ENOMEM;
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/*
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* We want to scale the number of MTTs with the size of the
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* system memory, since it makes sense to register a lot of
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* memory on a system with a lot of memory. As a heuristic,
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* make sure we have enough MTTs to cover twice the system
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* memory (with PAGE_SIZE entries).
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*
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* This number has to be a power of two and fit into 32 bits
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* due to device limitations, so cap this at 2^31 as well.
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* That limits us to 8TB of memory registration per HCA with
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* 4KB pages, which is probably OK for the next few months.
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*/
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si_meminfo(&si);
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request->num_mtt =
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roundup_pow_of_two(max_t(unsigned, request->num_mtt,
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2024-09-09 08:57:42 +00:00
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min(1UL << (31 - log_mtts_per_seg),
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si.totalram >> (log_mtts_per_seg - 1))));
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profile[MLX4_RES_QP].size = dev_cap->qpc_entry_sz;
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profile[MLX4_RES_RDMARC].size = dev_cap->rdmarc_entry_sz;
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profile[MLX4_RES_ALTC].size = dev_cap->altc_entry_sz;
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profile[MLX4_RES_AUXC].size = dev_cap->aux_entry_sz;
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profile[MLX4_RES_SRQ].size = dev_cap->srq_entry_sz;
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profile[MLX4_RES_CQ].size = dev_cap->cqc_entry_sz;
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profile[MLX4_RES_EQ].size = dev_cap->eqc_entry_sz;
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profile[MLX4_RES_DMPT].size = dev_cap->dmpt_entry_sz;
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profile[MLX4_RES_CMPT].size = dev_cap->cmpt_entry_sz;
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profile[MLX4_RES_MTT].size = dev_cap->mtt_entry_sz;
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profile[MLX4_RES_MCG].size = mlx4_get_mgm_entry_size(dev);
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profile[MLX4_RES_QP].num = request->num_qp;
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profile[MLX4_RES_RDMARC].num = request->num_qp * request->rdmarc_per_qp;
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profile[MLX4_RES_ALTC].num = request->num_qp;
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profile[MLX4_RES_AUXC].num = request->num_qp;
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profile[MLX4_RES_SRQ].num = request->num_srq;
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profile[MLX4_RES_CQ].num = request->num_cq;
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2024-09-09 08:57:42 +00:00
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profile[MLX4_RES_EQ].num = mlx4_is_mfunc(dev) ?
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dev->phys_caps.num_phys_eqs :
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min_t(unsigned, dev_cap->max_eqs, MAX_MSIX);
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profile[MLX4_RES_DMPT].num = request->num_mpt;
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profile[MLX4_RES_CMPT].num = MLX4_NUM_CMPTS;
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profile[MLX4_RES_MTT].num = request->num_mtt * (1 << log_mtts_per_seg);
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profile[MLX4_RES_MCG].num = request->num_mcg;
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for (i = 0; i < MLX4_RES_NUM; ++i) {
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profile[i].type = i;
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profile[i].num = roundup_pow_of_two(profile[i].num);
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profile[i].log_num = ilog2(profile[i].num);
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profile[i].size *= profile[i].num;
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profile[i].size = max(profile[i].size, (u64) PAGE_SIZE);
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}
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/*
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* Sort the resources in decreasing order of size. Since they
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* all have sizes that are powers of 2, we'll be able to keep
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* resources aligned to their size and pack them without gaps
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* using the sorted order.
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*/
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for (i = MLX4_RES_NUM; i > 0; --i)
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for (j = 1; j < i; ++j) {
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if (profile[j].size > profile[j - 1].size) {
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tmp = profile[j];
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profile[j] = profile[j - 1];
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profile[j - 1] = tmp;
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}
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}
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for (i = 0; i < MLX4_RES_NUM; ++i) {
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if (profile[i].size) {
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profile[i].start = total_size;
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total_size += profile[i].size;
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}
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if (total_size > dev_cap->max_icm_sz) {
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2024-09-09 08:57:42 +00:00
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mlx4_err(dev, "Profile requires 0x%llx bytes; won't fit in 0x%llx bytes of context memory\n",
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(unsigned long long) total_size,
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(unsigned long long) dev_cap->max_icm_sz);
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kfree(profile);
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return -ENOMEM;
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}
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if (profile[i].size)
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mlx4_dbg(dev, " profile[%2d] (%6s): 2^%02d entries @ 0x%10llx, size 0x%10llx\n",
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i, res_name[profile[i].type],
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profile[i].log_num,
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(unsigned long long) profile[i].start,
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(unsigned long long) profile[i].size);
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}
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mlx4_dbg(dev, "HCA context memory: reserving %d KB\n",
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(int) (total_size >> 10));
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for (i = 0; i < MLX4_RES_NUM; ++i) {
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switch (profile[i].type) {
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case MLX4_RES_QP:
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dev->caps.num_qps = profile[i].num;
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init_hca->qpc_base = profile[i].start;
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init_hca->log_num_qps = profile[i].log_num;
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break;
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case MLX4_RES_RDMARC:
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for (priv->qp_table.rdmarc_shift = 0;
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request->num_qp << priv->qp_table.rdmarc_shift < profile[i].num;
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++priv->qp_table.rdmarc_shift)
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; /* nothing */
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dev->caps.max_qp_dest_rdma = 1 << priv->qp_table.rdmarc_shift;
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priv->qp_table.rdmarc_base = (u32) profile[i].start;
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init_hca->rdmarc_base = profile[i].start;
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init_hca->log_rd_per_qp = priv->qp_table.rdmarc_shift;
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break;
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case MLX4_RES_ALTC:
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init_hca->altc_base = profile[i].start;
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break;
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case MLX4_RES_AUXC:
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init_hca->auxc_base = profile[i].start;
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break;
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case MLX4_RES_SRQ:
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dev->caps.num_srqs = profile[i].num;
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init_hca->srqc_base = profile[i].start;
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init_hca->log_num_srqs = profile[i].log_num;
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break;
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case MLX4_RES_CQ:
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dev->caps.num_cqs = profile[i].num;
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init_hca->cqc_base = profile[i].start;
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init_hca->log_num_cqs = profile[i].log_num;
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break;
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case MLX4_RES_EQ:
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dev->caps.num_eqs = roundup_pow_of_two(min_t(unsigned, dev_cap->max_eqs,
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MAX_MSIX));
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init_hca->eqc_base = profile[i].start;
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init_hca->log_num_eqs = ilog2(dev->caps.num_eqs);
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break;
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case MLX4_RES_DMPT:
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dev->caps.num_mpts = profile[i].num;
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priv->mr_table.mpt_base = profile[i].start;
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init_hca->dmpt_base = profile[i].start;
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init_hca->log_mpt_sz = profile[i].log_num;
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break;
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case MLX4_RES_CMPT:
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init_hca->cmpt_base = profile[i].start;
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break;
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case MLX4_RES_MTT:
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dev->caps.num_mtts = profile[i].num;
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priv->mr_table.mtt_base = profile[i].start;
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init_hca->mtt_base = profile[i].start;
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break;
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case MLX4_RES_MCG:
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init_hca->mc_base = profile[i].start;
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init_hca->log_mc_entry_sz =
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ilog2(mlx4_get_mgm_entry_size(dev));
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init_hca->log_mc_table_sz = profile[i].log_num;
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if (dev->caps.steering_mode ==
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MLX4_STEERING_MODE_DEVICE_MANAGED) {
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dev->caps.num_mgms = profile[i].num;
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} else {
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init_hca->log_mc_hash_sz =
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profile[i].log_num - 1;
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dev->caps.num_mgms = profile[i].num >> 1;
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dev->caps.num_amgms = profile[i].num >> 1;
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}
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2024-09-09 08:52:07 +00:00
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break;
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default:
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break;
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}
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}
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/*
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* PDs don't take any HCA memory, but we assign them as part
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* of the HCA profile anyway.
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*/
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dev->caps.num_pds = MLX4_NUM_PDS;
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kfree(profile);
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return total_size;
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}
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