304 lines
10 KiB
C
304 lines
10 KiB
C
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/*******************************************************************************
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*
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* Intel Ethernet Controller XL710 Family Linux Driver
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* Copyright(c) 2013 - 2014 Intel Corporation.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program. If not, see <http://www.gnu.org/licenses/>.
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*
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* The full GNU General Public License is included in this distribution in
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* the file called "COPYING".
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*
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* Contact Information:
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* e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
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* Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
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*
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******************************************************************************/
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#ifndef _I40E_TXRX_H_
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#define _I40E_TXRX_H_
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/* Interrupt Throttling and Rate Limiting Goodies */
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#define I40E_MAX_ITR 0x0FF0 /* reg uses 2 usec resolution */
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#define I40E_MIN_ITR 0x0004 /* reg uses 2 usec resolution */
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#define I40E_MAX_IRATE 0x03F
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#define I40E_MIN_IRATE 0x001
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#define I40E_IRATE_USEC_RESOLUTION 4
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#define I40E_ITR_100K 0x0005
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#define I40E_ITR_20K 0x0019
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#define I40E_ITR_8K 0x003E
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#define I40E_ITR_4K 0x007A
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#define I40E_ITR_RX_DEF I40E_ITR_8K
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#define I40E_ITR_TX_DEF I40E_ITR_4K
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#define I40E_ITR_DYNAMIC 0x8000 /* use top bit as a flag */
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#define I40E_MIN_INT_RATE 250 /* ~= 1000000 / (I40E_MAX_ITR * 2) */
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#define I40E_MAX_INT_RATE 500000 /* == 1000000 / (I40E_MIN_ITR * 2) */
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#define I40E_DEFAULT_IRQ_WORK 256
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#define ITR_TO_REG(setting) ((setting & ~I40E_ITR_DYNAMIC) >> 1)
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#define ITR_IS_DYNAMIC(setting) (!!(setting & I40E_ITR_DYNAMIC))
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#define ITR_REG_TO_USEC(itr_reg) (itr_reg << 1)
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#define I40E_QUEUE_END_OF_LIST 0x7FF
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/* this enum matches hardware bits and is meant to be used by DYN_CTLN
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* registers and QINT registers or more generally anywhere in the manual
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* mentioning ITR_INDX, ITR_NONE cannot be used as an index 'n' into any
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* register but instead is a special value meaning "don't update" ITR0/1/2.
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*/
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enum i40e_dyn_idx_t {
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I40E_IDX_ITR0 = 0,
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I40E_IDX_ITR1 = 1,
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I40E_IDX_ITR2 = 2,
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I40E_ITR_NONE = 3 /* ITR_NONE must not be used as an index */
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};
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/* these are indexes into ITRN registers */
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#define I40E_RX_ITR I40E_IDX_ITR0
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#define I40E_TX_ITR I40E_IDX_ITR1
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#define I40E_PE_ITR I40E_IDX_ITR2
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/* Supported RSS offloads */
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#define I40E_DEFAULT_RSS_HENA ( \
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((u64)1 << I40E_FILTER_PCTYPE_NONF_IPV4_UDP) | \
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((u64)1 << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP) | \
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((u64)1 << I40E_FILTER_PCTYPE_NONF_IPV4_TCP) | \
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((u64)1 << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER) | \
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((u64)1 << I40E_FILTER_PCTYPE_FRAG_IPV4) | \
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((u64)1 << I40E_FILTER_PCTYPE_NONF_IPV6_UDP) | \
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((u64)1 << I40E_FILTER_PCTYPE_NONF_IPV6_TCP) | \
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((u64)1 << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP) | \
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((u64)1 << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER) | \
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((u64)1 << I40E_FILTER_PCTYPE_FRAG_IPV6) | \
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((u64)1 << I40E_FILTER_PCTYPE_L2_PAYLOAD))
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/* Supported Rx Buffer Sizes */
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#define I40E_RXBUFFER_512 512 /* Used for packet split */
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#define I40E_RXBUFFER_2048 2048
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#define I40E_RXBUFFER_3072 3072 /* For FCoE MTU of 2158 */
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#define I40E_RXBUFFER_4096 4096
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#define I40E_RXBUFFER_8192 8192
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#define I40E_MAX_RXBUFFER 9728 /* largest size for single descriptor */
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/* NOTE: netdev_alloc_skb reserves up to 64 bytes, NET_IP_ALIGN means we
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* reserve 2 more, and skb_shared_info adds an additional 384 bytes more,
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* this adds up to 512 bytes of extra data meaning the smallest allocation
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* we could have is 1K.
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* i.e. RXBUFFER_512 --> size-1024 slab
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*/
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#define I40E_RX_HDR_SIZE I40E_RXBUFFER_512
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/* How many Rx Buffers do we bundle into one write to the hardware ? */
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#define I40E_RX_BUFFER_WRITE 16 /* Must be power of 2 */
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#define I40E_RX_NEXT_DESC(r, i, n) \
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do { \
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(i)++; \
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if ((i) == (r)->count) \
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i = 0; \
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(n) = I40E_RX_DESC((r), (i)); \
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} while (0)
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#define I40E_RX_NEXT_DESC_PREFETCH(r, i, n) \
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do { \
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I40E_RX_NEXT_DESC((r), (i), (n)); \
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prefetch((n)); \
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} while (0)
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#define i40e_rx_desc i40e_32byte_rx_desc
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#define I40E_MIN_TX_LEN 17
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#define I40E_MAX_DATA_PER_TXD 8192
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/* Tx Descriptors needed, worst case */
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#define TXD_USE_COUNT(S) DIV_ROUND_UP((S), I40E_MAX_DATA_PER_TXD)
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#define DESC_NEEDED (MAX_SKB_FRAGS + 4)
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#define I40E_MIN_DESC_PENDING 4
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#define I40E_TX_FLAGS_CSUM (u32)(1)
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#define I40E_TX_FLAGS_HW_VLAN (u32)(1 << 1)
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#define I40E_TX_FLAGS_SW_VLAN (u32)(1 << 2)
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#define I40E_TX_FLAGS_TSO (u32)(1 << 3)
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#define I40E_TX_FLAGS_IPV4 (u32)(1 << 4)
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#define I40E_TX_FLAGS_IPV6 (u32)(1 << 5)
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#define I40E_TX_FLAGS_FCCRC (u32)(1 << 6)
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#define I40E_TX_FLAGS_FSO (u32)(1 << 7)
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#define I40E_TX_FLAGS_TSYN (u32)(1 << 8)
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#define I40E_TX_FLAGS_FD_SB (u32)(1 << 9)
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#define I40E_TX_FLAGS_VLAN_MASK 0xffff0000
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#define I40E_TX_FLAGS_VLAN_PRIO_MASK 0xe0000000
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#define I40E_TX_FLAGS_VLAN_PRIO_SHIFT 29
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#define I40E_TX_FLAGS_VLAN_SHIFT 16
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struct i40e_tx_buffer {
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struct i40e_tx_desc *next_to_watch;
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unsigned long time_stamp;
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union {
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struct sk_buff *skb;
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void *raw_buf;
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};
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unsigned int bytecount;
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unsigned short gso_segs;
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DEFINE_DMA_UNMAP_ADDR(dma);
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DEFINE_DMA_UNMAP_LEN(len);
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u32 tx_flags;
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};
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struct i40e_rx_buffer {
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struct sk_buff *skb;
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dma_addr_t dma;
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struct page *page;
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dma_addr_t page_dma;
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unsigned int page_offset;
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};
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struct i40e_queue_stats {
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u64 packets;
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u64 bytes;
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};
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struct i40e_tx_queue_stats {
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u64 restart_queue;
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u64 tx_busy;
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u64 tx_done_old;
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};
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struct i40e_rx_queue_stats {
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u64 non_eop_descs;
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u64 alloc_page_failed;
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u64 alloc_buff_failed;
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};
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enum i40e_ring_state_t {
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__I40E_TX_FDIR_INIT_DONE,
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__I40E_TX_XPS_INIT_DONE,
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__I40E_TX_DETECT_HANG,
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__I40E_HANG_CHECK_ARMED,
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__I40E_RX_PS_ENABLED,
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__I40E_RX_16BYTE_DESC_ENABLED,
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};
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#define ring_is_ps_enabled(ring) \
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test_bit(__I40E_RX_PS_ENABLED, &(ring)->state)
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#define set_ring_ps_enabled(ring) \
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set_bit(__I40E_RX_PS_ENABLED, &(ring)->state)
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#define clear_ring_ps_enabled(ring) \
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clear_bit(__I40E_RX_PS_ENABLED, &(ring)->state)
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#define check_for_tx_hang(ring) \
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test_bit(__I40E_TX_DETECT_HANG, &(ring)->state)
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#define set_check_for_tx_hang(ring) \
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set_bit(__I40E_TX_DETECT_HANG, &(ring)->state)
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#define clear_check_for_tx_hang(ring) \
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clear_bit(__I40E_TX_DETECT_HANG, &(ring)->state)
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#define ring_is_16byte_desc_enabled(ring) \
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test_bit(__I40E_RX_16BYTE_DESC_ENABLED, &(ring)->state)
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#define set_ring_16byte_desc_enabled(ring) \
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set_bit(__I40E_RX_16BYTE_DESC_ENABLED, &(ring)->state)
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#define clear_ring_16byte_desc_enabled(ring) \
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clear_bit(__I40E_RX_16BYTE_DESC_ENABLED, &(ring)->state)
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/* struct that defines a descriptor ring, associated with a VSI */
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struct i40e_ring {
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struct i40e_ring *next; /* pointer to next ring in q_vector */
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void *desc; /* Descriptor ring memory */
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struct device *dev; /* Used for DMA mapping */
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struct net_device *netdev; /* netdev ring maps to */
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union {
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struct i40e_tx_buffer *tx_bi;
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struct i40e_rx_buffer *rx_bi;
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};
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unsigned long state;
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u16 queue_index; /* Queue number of ring */
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u8 dcb_tc; /* Traffic class of ring */
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u8 __iomem *tail;
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u16 count; /* Number of descriptors */
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u16 reg_idx; /* HW register index of the ring */
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u16 rx_hdr_len;
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u16 rx_buf_len;
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u8 dtype;
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#define I40E_RX_DTYPE_NO_SPLIT 0
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#define I40E_RX_DTYPE_SPLIT_ALWAYS 1
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#define I40E_RX_DTYPE_HEADER_SPLIT 2
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u8 hsplit;
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#define I40E_RX_SPLIT_L2 0x1
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#define I40E_RX_SPLIT_IP 0x2
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#define I40E_RX_SPLIT_TCP_UDP 0x4
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#define I40E_RX_SPLIT_SCTP 0x8
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/* used in interrupt processing */
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u16 next_to_use;
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u16 next_to_clean;
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u8 atr_sample_rate;
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u8 atr_count;
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unsigned long last_rx_timestamp;
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bool ring_active; /* is ring online or not */
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/* stats structs */
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struct i40e_queue_stats stats;
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struct u64_stats_sync syncp;
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union {
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struct i40e_tx_queue_stats tx_stats;
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struct i40e_rx_queue_stats rx_stats;
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};
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unsigned int size; /* length of descriptor ring in bytes */
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dma_addr_t dma; /* physical address of ring */
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struct i40e_vsi *vsi; /* Backreference to associated VSI */
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struct i40e_q_vector *q_vector; /* Backreference to associated vector */
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struct rcu_head rcu; /* to avoid race on free */
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} ____cacheline_internodealigned_in_smp;
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enum i40e_latency_range {
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I40E_LOWEST_LATENCY = 0,
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I40E_LOW_LATENCY = 1,
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I40E_BULK_LATENCY = 2,
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};
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struct i40e_ring_container {
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/* array of pointers to rings */
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struct i40e_ring *ring;
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unsigned int total_bytes; /* total bytes processed this int */
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unsigned int total_packets; /* total packets processed this int */
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u16 count;
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enum i40e_latency_range latency_range;
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u16 itr;
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};
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/* iterator for handling rings in ring container */
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#define i40e_for_each_ring(pos, head) \
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for (pos = (head).ring; pos != NULL; pos = pos->next)
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void i40e_alloc_rx_buffers(struct i40e_ring *rxr, u16 cleaned_count);
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netdev_tx_t i40e_lan_xmit_frame(struct sk_buff *skb, struct net_device *netdev);
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void i40e_clean_tx_ring(struct i40e_ring *tx_ring);
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void i40e_clean_rx_ring(struct i40e_ring *rx_ring);
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int i40e_setup_tx_descriptors(struct i40e_ring *tx_ring);
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int i40e_setup_rx_descriptors(struct i40e_ring *rx_ring);
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void i40e_free_tx_resources(struct i40e_ring *tx_ring);
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void i40e_free_rx_resources(struct i40e_ring *rx_ring);
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int i40e_napi_poll(struct napi_struct *napi, int budget);
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#ifdef I40E_FCOE
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void i40e_tx_map(struct i40e_ring *tx_ring, struct sk_buff *skb,
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struct i40e_tx_buffer *first, u32 tx_flags,
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const u8 hdr_len, u32 td_cmd, u32 td_offset);
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int i40e_maybe_stop_tx(struct i40e_ring *tx_ring, int size);
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int i40e_xmit_descriptor_count(struct sk_buff *skb, struct i40e_ring *tx_ring);
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int i40e_tx_prepare_vlan_flags(struct sk_buff *skb,
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struct i40e_ring *tx_ring, u32 *flags);
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#endif
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#endif /* _I40E_TXRX_H_ */
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