582 lines
19 KiB
C
582 lines
19 KiB
C
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/*
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* Copyright (c) 2013 Johannes Berg <johannes@sipsolutions.net>
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*
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* This file is free software: you may copy, redistribute and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation, either version 2 of the License, or (at your
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* option) any later version.
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*
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* This file is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*
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* This file incorporates work covered by the following copyright and
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* permission notice:
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*
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* Copyright (c) 2012 Qualcomm Atheros, Inc.
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*/
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#ifndef ALX_HW_H_
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#define ALX_HW_H_
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#include <linux/types.h>
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#include <linux/mdio.h>
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#include <linux/pci.h>
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#include "reg.h"
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/* Transmit Packet Descriptor, contains 4 32-bit words.
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*
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* 31 16 0
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* +----------------+----------------+
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* | vlan-tag | buf length |
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* +----------------+----------------+
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* | Word 1 |
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* +----------------+----------------+
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* | Word 2: buf addr lo |
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* +----------------+----------------+
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* | Word 3: buf addr hi |
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* +----------------+----------------+
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*
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* Word 2 and 3 combine to form a 64-bit buffer address
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*
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* Word 1 has three forms, depending on the state of bit 8/12/13:
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* if bit8 =='1', the definition is just for custom checksum offload.
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* if bit8 == '0' && bit12 == '1' && bit13 == '1', the *FIRST* descriptor
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* for the skb is special for LSO V2, Word 2 become total skb length ,
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* Word 3 is meaningless.
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* other condition, the definition is for general skb or ip/tcp/udp
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* checksum or LSO(TSO) offload.
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*
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* Here is the depiction:
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*
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* 0-+ 0-+
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* 1 | 1 |
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* 2 | 2 |
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* 3 | Payload offset 3 | L4 header offset
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* 4 | (7:0) 4 | (7:0)
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* 5 | 5 |
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* 6 | 6 |
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* 7-+ 7-+
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* 8 Custom csum enable = 1 8 Custom csum enable = 0
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* 9 General IPv4 checksum 9 General IPv4 checksum
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* 10 General TCP checksum 10 General TCP checksum
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* 11 General UDP checksum 11 General UDP checksum
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* 12 Large Send Segment enable 12 Large Send Segment enable
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* 13 Large Send Segment type 13 Large Send Segment type
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* 14 VLAN tagged 14 VLAN tagged
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* 15 Insert VLAN tag 15 Insert VLAN tag
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* 16 IPv4 packet 16 IPv4 packet
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* 17 Ethernet frame type 17 Ethernet frame type
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* 18-+ 18-+
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* 19 | 19 |
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* 20 | 20 |
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* 21 | Custom csum offset 21 |
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* 22 | (25:18) 22 |
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* 23 | 23 | MSS (30:18)
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* 24 | 24 |
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* 25-+ 25 |
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* 26-+ 26 |
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* 27 | 27 |
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* 28 | Reserved 28 |
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* 29 | 29 |
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* 30-+ 30-+
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* 31 End of packet 31 End of packet
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*/
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struct alx_txd {
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__le16 len;
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__le16 vlan_tag;
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__le32 word1;
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union {
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__le64 addr;
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struct {
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__le32 pkt_len;
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__le32 resvd;
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} l;
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} adrl;
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} __packed;
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/* tpd word 1 */
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#define TPD_CXSUMSTART_MASK 0x00FF
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#define TPD_CXSUMSTART_SHIFT 0
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#define TPD_L4HDROFFSET_MASK 0x00FF
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#define TPD_L4HDROFFSET_SHIFT 0
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#define TPD_CXSUM_EN_MASK 0x0001
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#define TPD_CXSUM_EN_SHIFT 8
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#define TPD_IP_XSUM_MASK 0x0001
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#define TPD_IP_XSUM_SHIFT 9
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#define TPD_TCP_XSUM_MASK 0x0001
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#define TPD_TCP_XSUM_SHIFT 10
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#define TPD_UDP_XSUM_MASK 0x0001
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#define TPD_UDP_XSUM_SHIFT 11
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#define TPD_LSO_EN_MASK 0x0001
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#define TPD_LSO_EN_SHIFT 12
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#define TPD_LSO_V2_MASK 0x0001
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#define TPD_LSO_V2_SHIFT 13
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#define TPD_VLTAGGED_MASK 0x0001
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#define TPD_VLTAGGED_SHIFT 14
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#define TPD_INS_VLTAG_MASK 0x0001
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#define TPD_INS_VLTAG_SHIFT 15
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#define TPD_IPV4_MASK 0x0001
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#define TPD_IPV4_SHIFT 16
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#define TPD_ETHTYPE_MASK 0x0001
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#define TPD_ETHTYPE_SHIFT 17
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#define TPD_CXSUMOFFSET_MASK 0x00FF
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#define TPD_CXSUMOFFSET_SHIFT 18
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#define TPD_MSS_MASK 0x1FFF
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#define TPD_MSS_SHIFT 18
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#define TPD_EOP_MASK 0x0001
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#define TPD_EOP_SHIFT 31
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#define DESC_GET(_x, _name) ((_x) >> _name##SHIFT & _name##MASK)
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/* Receive Free Descriptor */
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struct alx_rfd {
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__le64 addr; /* data buffer address, length is
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* declared in register --- every
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* buffer has the same size
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*/
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} __packed;
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/* Receive Return Descriptor, contains 4 32-bit words.
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*
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* 31 16 0
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* +----------------+----------------+
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* | Word 0 |
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* +----------------+----------------+
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* | Word 1: RSS Hash value |
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* +----------------+----------------+
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* | Word 2 |
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* +----------------+----------------+
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* | Word 3 |
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* +----------------+----------------+
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*
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* Word 0 depiction & Word 2 depiction:
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*
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* 0--+ 0--+
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* 1 | 1 |
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* 2 | 2 |
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* 3 | 3 |
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* 4 | 4 |
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* 5 | 5 |
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* 6 | 6 |
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* 7 | IP payload checksum 7 | VLAN tag
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* 8 | (15:0) 8 | (15:0)
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* 9 | 9 |
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* 10 | 10 |
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* 11 | 11 |
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* 12 | 12 |
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* 13 | 13 |
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* 14 | 14 |
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* 15-+ 15-+
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* 16-+ 16-+
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* 17 | Number of RFDs 17 |
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* 18 | (19:16) 18 |
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* 19-+ 19 | Protocol ID
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* 20-+ 20 | (23:16)
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* 21 | 21 |
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* 22 | 22 |
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* 23 | 23-+
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* 24 | 24 | Reserved
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* 25 | Start index of RFD-ring 25-+
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* 26 | (31:20) 26 | RSS Q-num (27:25)
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* 27 | 27-+
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* 28 | 28-+
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* 29 | 29 | RSS Hash algorithm
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* 30 | 30 | (31:28)
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* 31-+ 31-+
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*
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* Word 3 depiction:
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*
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* 0--+
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* 1 |
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* 2 |
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* 3 |
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* 4 |
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* 5 |
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* 6 |
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* 7 | Packet length (include FCS)
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* 8 | (13:0)
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* 9 |
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* 10 |
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* 11 |
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* 12 |
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* 13-+
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* 14 L4 Header checksum error
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* 15 IPv4 checksum error
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* 16 VLAN tagged
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* 17-+
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* 18 | Protocol ID (19:17)
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* 19-+
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* 20 Receive error summary
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* 21 FCS(CRC) error
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* 22 Frame alignment error
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* 23 Truncated packet
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* 24 Runt packet
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* 25 Incomplete packet due to insufficient rx-desc
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* 26 Broadcast packet
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* 27 Multicast packet
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* 28 Ethernet type (EII or 802.3)
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* 29 FIFO overflow
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* 30 Length error (for 802.3, length field mismatch with actual len)
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* 31 Updated, indicate to driver that this RRD is refreshed.
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*/
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struct alx_rrd {
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__le32 word0;
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__le32 rss_hash;
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__le32 word2;
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__le32 word3;
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} __packed;
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/* rrd word 0 */
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#define RRD_XSUM_MASK 0xFFFF
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#define RRD_XSUM_SHIFT 0
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#define RRD_NOR_MASK 0x000F
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#define RRD_NOR_SHIFT 16
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#define RRD_SI_MASK 0x0FFF
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#define RRD_SI_SHIFT 20
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/* rrd word 2 */
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#define RRD_VLTAG_MASK 0xFFFF
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#define RRD_VLTAG_SHIFT 0
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#define RRD_PID_MASK 0x00FF
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#define RRD_PID_SHIFT 16
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/* non-ip packet */
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#define RRD_PID_NONIP 0
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/* ipv4(only) */
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#define RRD_PID_IPV4 1
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/* tcp/ipv6 */
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#define RRD_PID_IPV6TCP 2
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/* tcp/ipv4 */
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#define RRD_PID_IPV4TCP 3
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/* udp/ipv6 */
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#define RRD_PID_IPV6UDP 4
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/* udp/ipv4 */
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#define RRD_PID_IPV4UDP 5
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/* ipv6(only) */
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#define RRD_PID_IPV6 6
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/* LLDP packet */
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#define RRD_PID_LLDP 7
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/* 1588 packet */
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#define RRD_PID_1588 8
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#define RRD_RSSQ_MASK 0x0007
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#define RRD_RSSQ_SHIFT 25
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#define RRD_RSSALG_MASK 0x000F
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#define RRD_RSSALG_SHIFT 28
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#define RRD_RSSALG_TCPV6 0x1
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#define RRD_RSSALG_IPV6 0x2
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#define RRD_RSSALG_TCPV4 0x4
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#define RRD_RSSALG_IPV4 0x8
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/* rrd word 3 */
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#define RRD_PKTLEN_MASK 0x3FFF
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#define RRD_PKTLEN_SHIFT 0
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#define RRD_ERR_L4_MASK 0x0001
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#define RRD_ERR_L4_SHIFT 14
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#define RRD_ERR_IPV4_MASK 0x0001
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#define RRD_ERR_IPV4_SHIFT 15
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#define RRD_VLTAGGED_MASK 0x0001
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#define RRD_VLTAGGED_SHIFT 16
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#define RRD_OLD_PID_MASK 0x0007
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#define RRD_OLD_PID_SHIFT 17
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#define RRD_ERR_RES_MASK 0x0001
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#define RRD_ERR_RES_SHIFT 20
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#define RRD_ERR_FCS_MASK 0x0001
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#define RRD_ERR_FCS_SHIFT 21
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#define RRD_ERR_FAE_MASK 0x0001
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#define RRD_ERR_FAE_SHIFT 22
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#define RRD_ERR_TRUNC_MASK 0x0001
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#define RRD_ERR_TRUNC_SHIFT 23
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#define RRD_ERR_RUNT_MASK 0x0001
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#define RRD_ERR_RUNT_SHIFT 24
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#define RRD_ERR_ICMP_MASK 0x0001
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#define RRD_ERR_ICMP_SHIFT 25
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#define RRD_BCAST_MASK 0x0001
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#define RRD_BCAST_SHIFT 26
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#define RRD_MCAST_MASK 0x0001
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#define RRD_MCAST_SHIFT 27
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#define RRD_ETHTYPE_MASK 0x0001
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#define RRD_ETHTYPE_SHIFT 28
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#define RRD_ERR_FIFOV_MASK 0x0001
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#define RRD_ERR_FIFOV_SHIFT 29
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#define RRD_ERR_LEN_MASK 0x0001
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#define RRD_ERR_LEN_SHIFT 30
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#define RRD_UPDATED_MASK 0x0001
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#define RRD_UPDATED_SHIFT 31
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#define ALX_MAX_SETUP_LNK_CYCLE 50
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/* for FlowControl */
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#define ALX_FC_RX 0x01
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#define ALX_FC_TX 0x02
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#define ALX_FC_ANEG 0x04
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/* for sleep control */
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#define ALX_SLEEP_WOL_PHY 0x00000001
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#define ALX_SLEEP_WOL_MAGIC 0x00000002
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#define ALX_SLEEP_CIFS 0x00000004
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#define ALX_SLEEP_ACTIVE (ALX_SLEEP_WOL_PHY | \
|
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ALX_SLEEP_WOL_MAGIC | \
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ALX_SLEEP_CIFS)
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/* for RSS hash type */
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||
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#define ALX_RSS_HASH_TYPE_IPV4 0x1
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#define ALX_RSS_HASH_TYPE_IPV4_TCP 0x2
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||
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#define ALX_RSS_HASH_TYPE_IPV6 0x4
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#define ALX_RSS_HASH_TYPE_IPV6_TCP 0x8
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#define ALX_RSS_HASH_TYPE_ALL (ALX_RSS_HASH_TYPE_IPV4 | \
|
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ALX_RSS_HASH_TYPE_IPV4_TCP | \
|
||
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ALX_RSS_HASH_TYPE_IPV6 | \
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ALX_RSS_HASH_TYPE_IPV6_TCP)
|
||
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#define ALX_DEF_RXBUF_SIZE 1536
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||
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#define ALX_MAX_JUMBO_PKT_SIZE (9*1024)
|
||
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#define ALX_MAX_TSO_PKT_SIZE (7*1024)
|
||
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#define ALX_MAX_FRAME_SIZE ALX_MAX_JUMBO_PKT_SIZE
|
||
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#define ALX_MIN_FRAME_SIZE 68
|
||
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#define ALX_RAW_MTU(_mtu) (_mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN)
|
||
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|
||
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#define ALX_MAX_RX_QUEUES 8
|
||
|
|
#define ALX_MAX_TX_QUEUES 4
|
||
|
|
#define ALX_MAX_HANDLED_INTRS 5
|
||
|
|
|
||
|
|
#define ALX_ISR_MISC (ALX_ISR_PCIE_LNKDOWN | \
|
||
|
|
ALX_ISR_DMAW | \
|
||
|
|
ALX_ISR_DMAR | \
|
||
|
|
ALX_ISR_SMB | \
|
||
|
|
ALX_ISR_MANU | \
|
||
|
|
ALX_ISR_TIMER)
|
||
|
|
|
||
|
|
#define ALX_ISR_FATAL (ALX_ISR_PCIE_LNKDOWN | \
|
||
|
|
ALX_ISR_DMAW | ALX_ISR_DMAR)
|
||
|
|
|
||
|
|
#define ALX_ISR_ALERT (ALX_ISR_RXF_OV | \
|
||
|
|
ALX_ISR_TXF_UR | \
|
||
|
|
ALX_ISR_RFD_UR)
|
||
|
|
|
||
|
|
#define ALX_ISR_ALL_QUEUES (ALX_ISR_TX_Q0 | \
|
||
|
|
ALX_ISR_TX_Q1 | \
|
||
|
|
ALX_ISR_TX_Q2 | \
|
||
|
|
ALX_ISR_TX_Q3 | \
|
||
|
|
ALX_ISR_RX_Q0 | \
|
||
|
|
ALX_ISR_RX_Q1 | \
|
||
|
|
ALX_ISR_RX_Q2 | \
|
||
|
|
ALX_ISR_RX_Q3 | \
|
||
|
|
ALX_ISR_RX_Q4 | \
|
||
|
|
ALX_ISR_RX_Q5 | \
|
||
|
|
ALX_ISR_RX_Q6 | \
|
||
|
|
ALX_ISR_RX_Q7)
|
||
|
|
|
||
|
|
/* Statistics counters collected by the MAC
|
||
|
|
*
|
||
|
|
* The order of the fields must match the strings in alx_gstrings_stats
|
||
|
|
* All stats fields should be u64
|
||
|
|
* See ethtool.c
|
||
|
|
*/
|
||
|
|
struct alx_hw_stats {
|
||
|
|
/* rx */
|
||
|
|
u64 rx_ok; /* good RX packets */
|
||
|
|
u64 rx_bcast; /* good RX broadcast packets */
|
||
|
|
u64 rx_mcast; /* good RX multicast packets */
|
||
|
|
u64 rx_pause; /* RX pause frames */
|
||
|
|
u64 rx_ctrl; /* RX control packets other than pause frames */
|
||
|
|
u64 rx_fcs_err; /* RX packets with bad FCS */
|
||
|
|
u64 rx_len_err; /* RX packets with length != actual size */
|
||
|
|
u64 rx_byte_cnt; /* good bytes received. FCS is NOT included */
|
||
|
|
u64 rx_runt; /* RX packets < 64 bytes with good FCS */
|
||
|
|
u64 rx_frag; /* RX packets < 64 bytes with bad FCS */
|
||
|
|
u64 rx_sz_64B; /* 64 byte RX packets */
|
||
|
|
u64 rx_sz_127B; /* 65-127 byte RX packets */
|
||
|
|
u64 rx_sz_255B; /* 128-255 byte RX packets */
|
||
|
|
u64 rx_sz_511B; /* 256-511 byte RX packets */
|
||
|
|
u64 rx_sz_1023B; /* 512-1023 byte RX packets */
|
||
|
|
u64 rx_sz_1518B; /* 1024-1518 byte RX packets */
|
||
|
|
u64 rx_sz_max; /* 1519 byte to MTU RX packets */
|
||
|
|
u64 rx_ov_sz; /* truncated RX packets, size > MTU */
|
||
|
|
u64 rx_ov_rxf; /* frames dropped due to RX FIFO overflow */
|
||
|
|
u64 rx_ov_rrd; /* frames dropped due to RRD overflow */
|
||
|
|
u64 rx_align_err; /* alignment errors */
|
||
|
|
u64 rx_bc_byte_cnt; /* RX broadcast bytes, excluding FCS */
|
||
|
|
u64 rx_mc_byte_cnt; /* RX multicast bytes, excluding FCS */
|
||
|
|
u64 rx_err_addr; /* packets dropped due to address filtering */
|
||
|
|
|
||
|
|
/* tx */
|
||
|
|
u64 tx_ok; /* good TX packets */
|
||
|
|
u64 tx_bcast; /* good TX broadcast packets */
|
||
|
|
u64 tx_mcast; /* good TX multicast packets */
|
||
|
|
u64 tx_pause; /* TX pause frames */
|
||
|
|
u64 tx_exc_defer; /* TX packets deferred excessively */
|
||
|
|
u64 tx_ctrl; /* TX control frames, excluding pause frames */
|
||
|
|
u64 tx_defer; /* TX packets deferred */
|
||
|
|
u64 tx_byte_cnt; /* bytes transmitted, FCS is NOT included */
|
||
|
|
u64 tx_sz_64B; /* 64 byte TX packets */
|
||
|
|
u64 tx_sz_127B; /* 65-127 byte TX packets */
|
||
|
|
u64 tx_sz_255B; /* 128-255 byte TX packets */
|
||
|
|
u64 tx_sz_511B; /* 256-511 byte TX packets */
|
||
|
|
u64 tx_sz_1023B; /* 512-1023 byte TX packets */
|
||
|
|
u64 tx_sz_1518B; /* 1024-1518 byte TX packets */
|
||
|
|
u64 tx_sz_max; /* 1519 byte to MTU TX packets */
|
||
|
|
u64 tx_single_col; /* packets TX after a single collision */
|
||
|
|
u64 tx_multi_col; /* packets TX after multiple collisions */
|
||
|
|
u64 tx_late_col; /* TX packets with late collisions */
|
||
|
|
u64 tx_abort_col; /* TX packets aborted w/excessive collisions */
|
||
|
|
u64 tx_underrun; /* TX packets aborted due to TX FIFO underrun
|
||
|
|
* or TRD FIFO underrun
|
||
|
|
*/
|
||
|
|
u64 tx_trd_eop; /* reads beyond the EOP into the next frame
|
||
|
|
* when TRD was not written timely
|
||
|
|
*/
|
||
|
|
u64 tx_len_err; /* TX packets where length != actual size */
|
||
|
|
u64 tx_trunc; /* TX packets truncated due to size > MTU */
|
||
|
|
u64 tx_bc_byte_cnt; /* broadcast bytes transmitted, excluding FCS */
|
||
|
|
u64 tx_mc_byte_cnt; /* multicast bytes transmitted, excluding FCS */
|
||
|
|
u64 update;
|
||
|
|
};
|
||
|
|
|
||
|
|
|
||
|
|
/* maximum interrupt vectors for msix */
|
||
|
|
#define ALX_MAX_MSIX_INTRS 16
|
||
|
|
|
||
|
|
#define ALX_GET_FIELD(_data, _field) \
|
||
|
|
(((_data) >> _field ## _SHIFT) & _field ## _MASK)
|
||
|
|
|
||
|
|
#define ALX_SET_FIELD(_data, _field, _value) do { \
|
||
|
|
(_data) &= ~(_field ## _MASK << _field ## _SHIFT); \
|
||
|
|
(_data) |= ((_value) & _field ## _MASK) << _field ## _SHIFT;\
|
||
|
|
} while (0)
|
||
|
|
|
||
|
|
struct alx_hw {
|
||
|
|
struct pci_dev *pdev;
|
||
|
|
u8 __iomem *hw_addr;
|
||
|
|
|
||
|
|
/* current & permanent mac addr */
|
||
|
|
u8 mac_addr[ETH_ALEN];
|
||
|
|
u8 perm_addr[ETH_ALEN];
|
||
|
|
|
||
|
|
u16 mtu;
|
||
|
|
u16 imt;
|
||
|
|
u8 dma_chnl;
|
||
|
|
u8 max_dma_chnl;
|
||
|
|
/* tpd threshold to trig INT */
|
||
|
|
u32 ith_tpd;
|
||
|
|
u32 rx_ctrl;
|
||
|
|
u32 mc_hash[2];
|
||
|
|
|
||
|
|
u32 smb_timer;
|
||
|
|
/* SPEED_* + DUPLEX_*, SPEED_UNKNOWN if link is down */
|
||
|
|
int link_speed;
|
||
|
|
u8 duplex;
|
||
|
|
|
||
|
|
/* auto-neg advertisement or force mode config */
|
||
|
|
u8 flowctrl;
|
||
|
|
u32 adv_cfg;
|
||
|
|
|
||
|
|
spinlock_t mdio_lock;
|
||
|
|
struct mdio_if_info mdio;
|
||
|
|
u16 phy_id[2];
|
||
|
|
|
||
|
|
/* PHY link patch flag */
|
||
|
|
bool lnk_patch;
|
||
|
|
|
||
|
|
/* cumulated stats from the hardware (registers are cleared on read) */
|
||
|
|
struct alx_hw_stats stats;
|
||
|
|
};
|
||
|
|
|
||
|
|
static inline int alx_hw_revision(struct alx_hw *hw)
|
||
|
|
{
|
||
|
|
return hw->pdev->revision >> ALX_PCI_REVID_SHIFT;
|
||
|
|
}
|
||
|
|
|
||
|
|
static inline bool alx_hw_with_cr(struct alx_hw *hw)
|
||
|
|
{
|
||
|
|
return hw->pdev->revision & 1;
|
||
|
|
}
|
||
|
|
|
||
|
|
static inline bool alx_hw_giga(struct alx_hw *hw)
|
||
|
|
{
|
||
|
|
return hw->pdev->device & 1;
|
||
|
|
}
|
||
|
|
|
||
|
|
static inline void alx_write_mem8(struct alx_hw *hw, u32 reg, u8 val)
|
||
|
|
{
|
||
|
|
writeb(val, hw->hw_addr + reg);
|
||
|
|
}
|
||
|
|
|
||
|
|
static inline void alx_write_mem16(struct alx_hw *hw, u32 reg, u16 val)
|
||
|
|
{
|
||
|
|
writew(val, hw->hw_addr + reg);
|
||
|
|
}
|
||
|
|
|
||
|
|
static inline u16 alx_read_mem16(struct alx_hw *hw, u32 reg)
|
||
|
|
{
|
||
|
|
return readw(hw->hw_addr + reg);
|
||
|
|
}
|
||
|
|
|
||
|
|
static inline void alx_write_mem32(struct alx_hw *hw, u32 reg, u32 val)
|
||
|
|
{
|
||
|
|
writel(val, hw->hw_addr + reg);
|
||
|
|
}
|
||
|
|
|
||
|
|
static inline u32 alx_read_mem32(struct alx_hw *hw, u32 reg)
|
||
|
|
{
|
||
|
|
return readl(hw->hw_addr + reg);
|
||
|
|
}
|
||
|
|
|
||
|
|
static inline void alx_post_write(struct alx_hw *hw)
|
||
|
|
{
|
||
|
|
readl(hw->hw_addr);
|
||
|
|
}
|
||
|
|
|
||
|
|
int alx_get_perm_macaddr(struct alx_hw *hw, u8 *addr);
|
||
|
|
void alx_reset_phy(struct alx_hw *hw);
|
||
|
|
void alx_reset_pcie(struct alx_hw *hw);
|
||
|
|
void alx_enable_aspm(struct alx_hw *hw, bool l0s_en, bool l1_en);
|
||
|
|
int alx_setup_speed_duplex(struct alx_hw *hw, u32 ethadv, u8 flowctrl);
|
||
|
|
void alx_post_phy_link(struct alx_hw *hw);
|
||
|
|
int alx_read_phy_reg(struct alx_hw *hw, u16 reg, u16 *phy_data);
|
||
|
|
int alx_write_phy_reg(struct alx_hw *hw, u16 reg, u16 phy_data);
|
||
|
|
int alx_read_phy_ext(struct alx_hw *hw, u8 dev, u16 reg, u16 *pdata);
|
||
|
|
int alx_write_phy_ext(struct alx_hw *hw, u8 dev, u16 reg, u16 data);
|
||
|
|
int alx_read_phy_link(struct alx_hw *hw);
|
||
|
|
int alx_clear_phy_intr(struct alx_hw *hw);
|
||
|
|
void alx_cfg_mac_flowcontrol(struct alx_hw *hw, u8 fc);
|
||
|
|
void alx_start_mac(struct alx_hw *hw);
|
||
|
|
int alx_reset_mac(struct alx_hw *hw);
|
||
|
|
void alx_set_macaddr(struct alx_hw *hw, const u8 *addr);
|
||
|
|
bool alx_phy_configured(struct alx_hw *hw);
|
||
|
|
void alx_configure_basic(struct alx_hw *hw);
|
||
|
|
void alx_disable_rss(struct alx_hw *hw);
|
||
|
|
bool alx_get_phy_info(struct alx_hw *hw);
|
||
|
|
void alx_update_hw_stats(struct alx_hw *hw);
|
||
|
|
|
||
|
|
static inline u32 alx_speed_to_ethadv(int speed, u8 duplex)
|
||
|
|
{
|
||
|
|
if (speed == SPEED_1000 && duplex == DUPLEX_FULL)
|
||
|
|
return ADVERTISED_1000baseT_Full;
|
||
|
|
if (speed == SPEED_100 && duplex == DUPLEX_FULL)
|
||
|
|
return ADVERTISED_100baseT_Full;
|
||
|
|
if (speed == SPEED_100 && duplex== DUPLEX_HALF)
|
||
|
|
return ADVERTISED_100baseT_Half;
|
||
|
|
if (speed == SPEED_10 && duplex == DUPLEX_FULL)
|
||
|
|
return ADVERTISED_10baseT_Full;
|
||
|
|
if (speed == SPEED_10 && duplex == DUPLEX_HALF)
|
||
|
|
return ADVERTISED_10baseT_Half;
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
|
||
|
|
#endif
|