338 lines
8.9 KiB
C
338 lines
8.9 KiB
C
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/* Applied Micro X-Gene SoC Ethernet Driver
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*
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* Copyright (c) 2014, Applied Micro Circuits Corporation
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* Authors: Iyappan Subramanian <isubramanian@apm.com>
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* Keyur Chudgar <kchudgar@apm.com>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include "xgene_enet_main.h"
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#include "xgene_enet_hw.h"
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#include "xgene_enet_xgmac.h"
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static void xgene_enet_wr_csr(struct xgene_enet_pdata *pdata,
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u32 offset, u32 val)
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{
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void __iomem *addr = pdata->eth_csr_addr + offset;
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iowrite32(val, addr);
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}
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static void xgene_enet_wr_ring_if(struct xgene_enet_pdata *pdata,
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u32 offset, u32 val)
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{
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void __iomem *addr = pdata->eth_ring_if_addr + offset;
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iowrite32(val, addr);
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}
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static void xgene_enet_wr_diag_csr(struct xgene_enet_pdata *pdata,
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u32 offset, u32 val)
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{
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void __iomem *addr = pdata->eth_diag_csr_addr + offset;
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iowrite32(val, addr);
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}
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static bool xgene_enet_wr_indirect(void __iomem *addr, void __iomem *wr,
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void __iomem *cmd, void __iomem *cmd_done,
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u32 wr_addr, u32 wr_data)
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{
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u32 done;
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u8 wait = 10;
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iowrite32(wr_addr, addr);
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iowrite32(wr_data, wr);
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iowrite32(XGENE_ENET_WR_CMD, cmd);
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/* wait for write command to complete */
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while (!(done = ioread32(cmd_done)) && wait--)
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udelay(1);
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if (!done)
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return false;
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iowrite32(0, cmd);
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return true;
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}
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static void xgene_enet_wr_mac(struct xgene_enet_pdata *pdata,
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u32 wr_addr, u32 wr_data)
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{
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void __iomem *addr, *wr, *cmd, *cmd_done;
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addr = pdata->mcx_mac_addr + MAC_ADDR_REG_OFFSET;
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wr = pdata->mcx_mac_addr + MAC_WRITE_REG_OFFSET;
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cmd = pdata->mcx_mac_addr + MAC_COMMAND_REG_OFFSET;
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cmd_done = pdata->mcx_mac_addr + MAC_COMMAND_DONE_REG_OFFSET;
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if (!xgene_enet_wr_indirect(addr, wr, cmd, cmd_done, wr_addr, wr_data))
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netdev_err(pdata->ndev, "MCX mac write failed, addr: %04x\n",
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wr_addr);
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}
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static void xgene_enet_rd_csr(struct xgene_enet_pdata *pdata,
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u32 offset, u32 *val)
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{
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void __iomem *addr = pdata->eth_csr_addr + offset;
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*val = ioread32(addr);
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}
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static void xgene_enet_rd_diag_csr(struct xgene_enet_pdata *pdata,
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u32 offset, u32 *val)
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{
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void __iomem *addr = pdata->eth_diag_csr_addr + offset;
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*val = ioread32(addr);
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}
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static bool xgene_enet_rd_indirect(void __iomem *addr, void __iomem *rd,
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void __iomem *cmd, void __iomem *cmd_done,
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u32 rd_addr, u32 *rd_data)
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{
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u32 done;
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u8 wait = 10;
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iowrite32(rd_addr, addr);
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iowrite32(XGENE_ENET_RD_CMD, cmd);
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/* wait for read command to complete */
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while (!(done = ioread32(cmd_done)) && wait--)
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udelay(1);
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if (!done)
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return false;
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*rd_data = ioread32(rd);
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iowrite32(0, cmd);
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return true;
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}
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static void xgene_enet_rd_mac(struct xgene_enet_pdata *pdata,
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u32 rd_addr, u32 *rd_data)
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{
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void __iomem *addr, *rd, *cmd, *cmd_done;
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addr = pdata->mcx_mac_addr + MAC_ADDR_REG_OFFSET;
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rd = pdata->mcx_mac_addr + MAC_READ_REG_OFFSET;
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cmd = pdata->mcx_mac_addr + MAC_COMMAND_REG_OFFSET;
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cmd_done = pdata->mcx_mac_addr + MAC_COMMAND_DONE_REG_OFFSET;
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if (!xgene_enet_rd_indirect(addr, rd, cmd, cmd_done, rd_addr, rd_data))
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netdev_err(pdata->ndev, "MCX mac read failed, addr: %04x\n",
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rd_addr);
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}
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static int xgene_enet_ecc_init(struct xgene_enet_pdata *pdata)
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{
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struct net_device *ndev = pdata->ndev;
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u32 data;
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u8 wait = 10;
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xgene_enet_wr_diag_csr(pdata, ENET_CFG_MEM_RAM_SHUTDOWN_ADDR, 0x0);
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do {
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usleep_range(100, 110);
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xgene_enet_rd_diag_csr(pdata, ENET_BLOCK_MEM_RDY_ADDR, &data);
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} while ((data != 0xffffffff) && wait--);
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if (data != 0xffffffff) {
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netdev_err(ndev, "Failed to release memory from shutdown\n");
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return -ENODEV;
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}
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return 0;
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}
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static void xgene_enet_config_ring_if_assoc(struct xgene_enet_pdata *pdata)
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{
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xgene_enet_wr_ring_if(pdata, ENET_CFGSSQMIWQASSOC_ADDR, 0);
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xgene_enet_wr_ring_if(pdata, ENET_CFGSSQMIFPQASSOC_ADDR, 0);
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xgene_enet_wr_ring_if(pdata, ENET_CFGSSQMIQMLITEWQASSOC_ADDR, 0);
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xgene_enet_wr_ring_if(pdata, ENET_CFGSSQMIQMLITEFPQASSOC_ADDR, 0);
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}
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static void xgene_xgmac_reset(struct xgene_enet_pdata *pdata)
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{
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xgene_enet_wr_mac(pdata, AXGMAC_CONFIG_0, HSTMACRST);
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xgene_enet_wr_mac(pdata, AXGMAC_CONFIG_0, 0);
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}
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static void xgene_xgmac_set_mac_addr(struct xgene_enet_pdata *pdata)
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{
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u32 addr0, addr1;
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u8 *dev_addr = pdata->ndev->dev_addr;
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addr0 = (dev_addr[3] << 24) | (dev_addr[2] << 16) |
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(dev_addr[1] << 8) | dev_addr[0];
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addr1 = (dev_addr[5] << 24) | (dev_addr[4] << 16);
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xgene_enet_wr_mac(pdata, HSTMACADR_LSW_ADDR, addr0);
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xgene_enet_wr_mac(pdata, HSTMACADR_MSW_ADDR, addr1);
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}
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static u32 xgene_enet_link_status(struct xgene_enet_pdata *pdata)
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{
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u32 data;
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xgene_enet_rd_csr(pdata, XG_LINK_STATUS_ADDR, &data);
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return data;
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}
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static void xgene_xgmac_init(struct xgene_enet_pdata *pdata)
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{
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u32 data;
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xgene_xgmac_reset(pdata);
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xgene_enet_rd_mac(pdata, AXGMAC_CONFIG_1, &data);
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data |= HSTPPEN;
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data &= ~HSTLENCHK;
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xgene_enet_wr_mac(pdata, AXGMAC_CONFIG_1, data);
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xgene_enet_wr_mac(pdata, HSTMAXFRAME_LENGTH_ADDR, 0x06000600);
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xgene_xgmac_set_mac_addr(pdata);
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xgene_enet_rd_csr(pdata, XG_RSIF_CONFIG_REG_ADDR, &data);
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data |= CFG_RSIF_FPBUFF_TIMEOUT_EN;
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xgene_enet_wr_csr(pdata, XG_RSIF_CONFIG_REG_ADDR, data);
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xgene_enet_wr_csr(pdata, XG_CFG_BYPASS_ADDR, RESUME_TX);
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xgene_enet_wr_csr(pdata, XGENET_RX_DV_GATE_REG_0_ADDR, 0);
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xgene_enet_rd_csr(pdata, XG_ENET_SPARE_CFG_REG_ADDR, &data);
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data |= BIT(12);
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xgene_enet_wr_csr(pdata, XG_ENET_SPARE_CFG_REG_ADDR, data);
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xgene_enet_wr_csr(pdata, XG_ENET_SPARE_CFG_REG_1_ADDR, 0x82);
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}
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static void xgene_xgmac_rx_enable(struct xgene_enet_pdata *pdata)
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{
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u32 data;
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xgene_enet_rd_mac(pdata, AXGMAC_CONFIG_1, &data);
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xgene_enet_wr_mac(pdata, AXGMAC_CONFIG_1, data | HSTRFEN);
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}
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static void xgene_xgmac_tx_enable(struct xgene_enet_pdata *pdata)
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{
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u32 data;
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xgene_enet_rd_mac(pdata, AXGMAC_CONFIG_1, &data);
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xgene_enet_wr_mac(pdata, AXGMAC_CONFIG_1, data | HSTTFEN);
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}
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static void xgene_xgmac_rx_disable(struct xgene_enet_pdata *pdata)
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{
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u32 data;
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xgene_enet_rd_mac(pdata, AXGMAC_CONFIG_1, &data);
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xgene_enet_wr_mac(pdata, AXGMAC_CONFIG_1, data & ~HSTRFEN);
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}
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static void xgene_xgmac_tx_disable(struct xgene_enet_pdata *pdata)
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{
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u32 data;
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xgene_enet_rd_mac(pdata, AXGMAC_CONFIG_1, &data);
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xgene_enet_wr_mac(pdata, AXGMAC_CONFIG_1, data & ~HSTTFEN);
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}
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static int xgene_enet_reset(struct xgene_enet_pdata *pdata)
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{
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if (!xgene_ring_mgr_init(pdata))
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return -ENODEV;
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clk_prepare_enable(pdata->clk);
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clk_disable_unprepare(pdata->clk);
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clk_prepare_enable(pdata->clk);
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xgene_enet_ecc_init(pdata);
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xgene_enet_config_ring_if_assoc(pdata);
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return 0;
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}
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static void xgene_enet_xgcle_bypass(struct xgene_enet_pdata *pdata,
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u32 dst_ring_num, u16 bufpool_id)
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{
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u32 cb, fpsel;
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xgene_enet_rd_csr(pdata, XCLE_BYPASS_REG0_ADDR, &cb);
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cb |= CFG_CLE_BYPASS_EN0;
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CFG_CLE_IP_PROTOCOL0_SET(&cb, 3);
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xgene_enet_wr_csr(pdata, XCLE_BYPASS_REG0_ADDR, cb);
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fpsel = xgene_enet_ring_bufnum(bufpool_id) - 0x20;
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xgene_enet_rd_csr(pdata, XCLE_BYPASS_REG1_ADDR, &cb);
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CFG_CLE_DSTQID0_SET(&cb, dst_ring_num);
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CFG_CLE_FPSEL0_SET(&cb, fpsel);
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xgene_enet_wr_csr(pdata, XCLE_BYPASS_REG1_ADDR, cb);
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}
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static void xgene_enet_shutdown(struct xgene_enet_pdata *pdata)
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{
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clk_disable_unprepare(pdata->clk);
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}
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static void xgene_enet_link_state(struct work_struct *work)
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{
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struct xgene_enet_pdata *pdata = container_of(to_delayed_work(work),
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struct xgene_enet_pdata, link_work);
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struct net_device *ndev = pdata->ndev;
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u32 link_status, poll_interval;
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link_status = xgene_enet_link_status(pdata);
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if (link_status) {
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if (!netif_carrier_ok(ndev)) {
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netif_carrier_on(ndev);
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xgene_xgmac_init(pdata);
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xgene_xgmac_rx_enable(pdata);
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xgene_xgmac_tx_enable(pdata);
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netdev_info(ndev, "Link is Up - 10Gbps\n");
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}
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poll_interval = PHY_POLL_LINK_ON;
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} else {
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if (netif_carrier_ok(ndev)) {
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xgene_xgmac_rx_disable(pdata);
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xgene_xgmac_tx_disable(pdata);
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netif_carrier_off(ndev);
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netdev_info(ndev, "Link is Down\n");
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}
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poll_interval = PHY_POLL_LINK_OFF;
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}
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schedule_delayed_work(&pdata->link_work, poll_interval);
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}
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struct xgene_mac_ops xgene_xgmac_ops = {
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.init = xgene_xgmac_init,
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.reset = xgene_xgmac_reset,
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.rx_enable = xgene_xgmac_rx_enable,
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.tx_enable = xgene_xgmac_tx_enable,
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.rx_disable = xgene_xgmac_rx_disable,
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.tx_disable = xgene_xgmac_tx_disable,
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.set_mac_addr = xgene_xgmac_set_mac_addr,
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.link_state = xgene_enet_link_state
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};
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struct xgene_port_ops xgene_xgport_ops = {
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.reset = xgene_enet_reset,
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.cle_bypass = xgene_enet_xgcle_bypass,
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.shutdown = xgene_enet_shutdown,
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||
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|
};
|