330 lines
8.9 KiB
C
330 lines
8.9 KiB
C
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/* Applied Micro X-Gene SoC Ethernet Driver
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*
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* Copyright (c) 2014, Applied Micro Circuits Corporation
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* Authors: Iyappan Subramanian <isubramanian@apm.com>
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* Ravi Patel <rapatel@apm.com>
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* Keyur Chudgar <kchudgar@apm.com>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef __XGENE_ENET_HW_H__
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#define __XGENE_ENET_HW_H__
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#include "xgene_enet_main.h"
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struct xgene_enet_pdata;
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struct xgene_enet_stats;
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/* clears and then set bits */
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static inline void xgene_set_bits(u32 *dst, u32 val, u32 start, u32 len)
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{
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u32 end = start + len - 1;
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u32 mask = GENMASK(end, start);
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*dst &= ~mask;
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*dst |= (val << start) & mask;
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}
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static inline u32 xgene_get_bits(u32 val, u32 start, u32 end)
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{
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return (val & GENMASK(end, start)) >> start;
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}
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enum xgene_enet_rm {
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RM0,
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RM1,
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RM3 = 3
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};
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#define CSR_RING_ID 0x0008
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#define OVERWRITE BIT(31)
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#define IS_BUFFER_POOL BIT(20)
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#define PREFETCH_BUF_EN BIT(21)
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#define CSR_RING_ID_BUF 0x000c
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#define CSR_RING_NE_INT_MODE 0x017c
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#define CSR_RING_CONFIG 0x006c
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#define CSR_RING_WR_BASE 0x0070
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#define NUM_RING_CONFIG 5
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#define BUFPOOL_MODE 3
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#define INC_DEC_CMD_ADDR 0x002c
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#define UDP_HDR_SIZE 2
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#define BUF_LEN_CODE_2K 0x5000
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#define CREATE_MASK(pos, len) GENMASK((pos)+(len)-1, (pos))
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#define CREATE_MASK_ULL(pos, len) GENMASK_ULL((pos)+(len)-1, (pos))
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/* Empty slot soft signature */
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#define EMPTY_SLOT_INDEX 1
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#define EMPTY_SLOT ~0ULL
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#define WORK_DESC_SIZE 32
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#define BUFPOOL_DESC_SIZE 16
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#define RING_OWNER_MASK GENMASK(9, 6)
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#define RING_BUFNUM_MASK GENMASK(5, 0)
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#define SELTHRSH_POS 3
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#define SELTHRSH_LEN 3
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#define RINGADDRL_POS 5
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#define RINGADDRL_LEN 27
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#define RINGADDRH_POS 0
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#define RINGADDRH_LEN 6
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#define RINGSIZE_POS 23
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#define RINGSIZE_LEN 3
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#define RINGTYPE_POS 19
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#define RINGTYPE_LEN 2
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#define RINGMODE_POS 20
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#define RINGMODE_LEN 3
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#define RECOMTIMEOUTL_POS 28
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#define RECOMTIMEOUTL_LEN 3
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#define RECOMTIMEOUTH_POS 0
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#define RECOMTIMEOUTH_LEN 2
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#define NUMMSGSINQ_POS 1
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#define NUMMSGSINQ_LEN 16
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#define ACCEPTLERR BIT(19)
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#define QCOHERENT BIT(4)
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#define RECOMBBUF BIT(27)
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#define BLOCK_ETH_CSR_OFFSET 0x2000
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#define BLOCK_ETH_RING_IF_OFFSET 0x9000
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#define BLOCK_ETH_DIAG_CSR_OFFSET 0xD000
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#define BLOCK_ETH_MAC_OFFSET 0x0000
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#define BLOCK_ETH_MAC_CSR_OFFSET 0x2800
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#define CLKEN_ADDR 0xc208
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#define SRST_ADDR 0xc200
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#define MAC_ADDR_REG_OFFSET 0x00
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#define MAC_COMMAND_REG_OFFSET 0x04
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#define MAC_WRITE_REG_OFFSET 0x08
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#define MAC_READ_REG_OFFSET 0x0c
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#define MAC_COMMAND_DONE_REG_OFFSET 0x10
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#define MII_MGMT_CONFIG_ADDR 0x20
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#define MII_MGMT_COMMAND_ADDR 0x24
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#define MII_MGMT_ADDRESS_ADDR 0x28
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#define MII_MGMT_CONTROL_ADDR 0x2c
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#define MII_MGMT_STATUS_ADDR 0x30
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#define MII_MGMT_INDICATORS_ADDR 0x34
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#define BUSY_MASK BIT(0)
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#define READ_CYCLE_MASK BIT(0)
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#define PHY_CONTROL_SET(dst, val) xgene_set_bits(dst, val, 0, 16)
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#define ENET_SPARE_CFG_REG_ADDR 0x0750
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#define RSIF_CONFIG_REG_ADDR 0x0010
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#define RSIF_RAM_DBG_REG0_ADDR 0x0048
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#define RGMII_REG_0_ADDR 0x07e0
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#define CFG_LINK_AGGR_RESUME_0_ADDR 0x07c8
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#define DEBUG_REG_ADDR 0x0700
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#define CFG_BYPASS_ADDR 0x0294
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#define CLE_BYPASS_REG0_0_ADDR 0x0490
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#define CLE_BYPASS_REG1_0_ADDR 0x0494
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#define CFG_RSIF_FPBUFF_TIMEOUT_EN BIT(31)
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#define RESUME_TX BIT(0)
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#define CFG_SPEED_1250 BIT(24)
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#define TX_PORT0 BIT(0)
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#define CFG_BYPASS_UNISEC_TX BIT(2)
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#define CFG_BYPASS_UNISEC_RX BIT(1)
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#define CFG_CLE_BYPASS_EN0 BIT(31)
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#define CFG_TXCLK_MUXSEL0_SET(dst, val) xgene_set_bits(dst, val, 29, 3)
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#define CFG_CLE_IP_PROTOCOL0_SET(dst, val) xgene_set_bits(dst, val, 16, 2)
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#define CFG_CLE_DSTQID0_SET(dst, val) xgene_set_bits(dst, val, 0, 12)
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#define CFG_CLE_FPSEL0_SET(dst, val) xgene_set_bits(dst, val, 16, 4)
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#define CFG_MACMODE_SET(dst, val) xgene_set_bits(dst, val, 18, 2)
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#define CFG_WAITASYNCRD_SET(dst, val) xgene_set_bits(dst, val, 0, 16)
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#define CFG_CLE_DSTQID0(val) (val & GENMASK(11, 0))
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#define CFG_CLE_FPSEL0(val) ((val << 16) & GENMASK(19, 16))
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#define ICM_CONFIG0_REG_0_ADDR 0x0400
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#define ICM_CONFIG2_REG_0_ADDR 0x0410
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#define RX_DV_GATE_REG_0_ADDR 0x05fc
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#define TX_DV_GATE_EN0 BIT(2)
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#define RX_DV_GATE_EN0 BIT(1)
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#define RESUME_RX0 BIT(0)
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#define ENET_CFGSSQMIWQASSOC_ADDR 0xe0
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#define ENET_CFGSSQMIFPQASSOC_ADDR 0xdc
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#define ENET_CFGSSQMIQMLITEFPQASSOC_ADDR 0xf0
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#define ENET_CFGSSQMIQMLITEWQASSOC_ADDR 0xf4
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#define ENET_CFG_MEM_RAM_SHUTDOWN_ADDR 0x70
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#define ENET_BLOCK_MEM_RDY_ADDR 0x74
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#define MAC_CONFIG_1_ADDR 0x00
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#define MAC_CONFIG_2_ADDR 0x04
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#define MAX_FRAME_LEN_ADDR 0x10
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#define INTERFACE_CONTROL_ADDR 0x38
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#define STATION_ADDR0_ADDR 0x40
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#define STATION_ADDR1_ADDR 0x44
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#define PHY_ADDR_SET(dst, val) xgene_set_bits(dst, val, 8, 5)
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#define REG_ADDR_SET(dst, val) xgene_set_bits(dst, val, 0, 5)
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#define ENET_INTERFACE_MODE2_SET(dst, val) xgene_set_bits(dst, val, 8, 2)
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#define MGMT_CLOCK_SEL_SET(dst, val) xgene_set_bits(dst, val, 0, 3)
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#define SOFT_RESET1 BIT(31)
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#define TX_EN BIT(0)
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#define RX_EN BIT(2)
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#define ENET_LHD_MODE BIT(25)
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#define ENET_GHD_MODE BIT(26)
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#define FULL_DUPLEX2 BIT(0)
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#define SCAN_AUTO_INCR BIT(5)
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#define TBYT_ADDR 0x38
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#define TPKT_ADDR 0x39
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#define TDRP_ADDR 0x45
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#define TFCS_ADDR 0x47
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#define TUND_ADDR 0x4a
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#define TSO_IPPROTO_TCP 1
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#define USERINFO_POS 0
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#define USERINFO_LEN 32
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#define FPQNUM_POS 32
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#define FPQNUM_LEN 12
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#define LERR_POS 60
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#define LERR_LEN 3
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#define STASH_POS 52
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#define STASH_LEN 2
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#define BUFDATALEN_POS 48
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#define BUFDATALEN_LEN 12
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#define DATAADDR_POS 0
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#define DATAADDR_LEN 42
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#define COHERENT_POS 63
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#define HENQNUM_POS 48
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#define HENQNUM_LEN 12
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#define TYPESEL_POS 44
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#define TYPESEL_LEN 4
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#define ETHHDR_POS 12
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#define ETHHDR_LEN 8
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#define IC_POS 35 /* Insert CRC */
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#define TCPHDR_POS 0
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#define TCPHDR_LEN 6
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#define IPHDR_POS 6
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#define IPHDR_LEN 6
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#define EC_POS 22 /* Enable checksum */
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#define EC_LEN 1
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#define IS_POS 24 /* IP protocol select */
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#define IS_LEN 1
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#define TYPE_ETH_WORK_MESSAGE_POS 44
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struct xgene_enet_raw_desc {
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__le64 m0;
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__le64 m1;
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__le64 m2;
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__le64 m3;
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};
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struct xgene_enet_raw_desc16 {
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__le64 m0;
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__le64 m1;
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};
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static inline void xgene_enet_mark_desc_slot_empty(void *desc_slot_ptr)
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{
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__le64 *desc_slot = desc_slot_ptr;
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desc_slot[EMPTY_SLOT_INDEX] = cpu_to_le64(EMPTY_SLOT);
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}
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static inline bool xgene_enet_is_desc_slot_empty(void *desc_slot_ptr)
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{
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__le64 *desc_slot = desc_slot_ptr;
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return (desc_slot[EMPTY_SLOT_INDEX] == cpu_to_le64(EMPTY_SLOT));
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}
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enum xgene_enet_ring_cfgsize {
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RING_CFGSIZE_512B,
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RING_CFGSIZE_2KB,
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RING_CFGSIZE_16KB,
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RING_CFGSIZE_64KB,
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RING_CFGSIZE_512KB,
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RING_CFGSIZE_INVALID
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};
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enum xgene_enet_ring_type {
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RING_DISABLED,
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RING_REGULAR,
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RING_BUFPOOL
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};
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enum xgene_ring_owner {
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RING_OWNER_ETH0,
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RING_OWNER_CPU = 15,
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RING_OWNER_INVALID
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};
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enum xgene_enet_ring_bufnum {
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RING_BUFNUM_REGULAR = 0x0,
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RING_BUFNUM_BUFPOOL = 0x20,
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RING_BUFNUM_INVALID
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};
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enum xgene_enet_cmd {
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XGENE_ENET_WR_CMD = BIT(31),
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XGENE_ENET_RD_CMD = BIT(30)
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};
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enum xgene_enet_err_code {
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HBF_READ_DATA = 3,
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HBF_LL_READ = 4,
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BAD_WORK_MSG = 6,
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BUFPOOL_TIMEOUT = 15,
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INGRESS_CRC = 16,
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INGRESS_CHECKSUM = 17,
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INGRESS_TRUNC_FRAME = 18,
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INGRESS_PKT_LEN = 19,
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INGRESS_PKT_UNDER = 20,
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INGRESS_FIFO_OVERRUN = 21,
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INGRESS_CHECKSUM_COMPUTE = 26,
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ERR_CODE_INVALID
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};
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static inline enum xgene_ring_owner xgene_enet_ring_owner(u16 id)
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{
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return (id & RING_OWNER_MASK) >> 6;
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}
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static inline u8 xgene_enet_ring_bufnum(u16 id)
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{
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return id & RING_BUFNUM_MASK;
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}
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static inline bool xgene_enet_is_bufpool(u16 id)
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{
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return ((id & RING_BUFNUM_MASK) >= 0x20) ? true : false;
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}
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static inline u16 xgene_enet_get_numslots(u16 id, u32 size)
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{
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bool is_bufpool = xgene_enet_is_bufpool(id);
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return (is_bufpool) ? size / BUFPOOL_DESC_SIZE :
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size / WORK_DESC_SIZE;
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}
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struct xgene_enet_desc_ring *xgene_enet_setup_ring(
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struct xgene_enet_desc_ring *ring);
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void xgene_enet_clear_ring(struct xgene_enet_desc_ring *ring);
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void xgene_enet_parse_error(struct xgene_enet_desc_ring *ring,
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struct xgene_enet_pdata *pdata,
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enum xgene_enet_err_code status);
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int xgene_enet_mdio_config(struct xgene_enet_pdata *pdata);
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void xgene_enet_mdio_remove(struct xgene_enet_pdata *pdata);
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bool xgene_ring_mgr_init(struct xgene_enet_pdata *p);
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extern struct xgene_mac_ops xgene_gmac_ops;
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extern struct xgene_port_ops xgene_gport_ops;
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#endif /* __XGENE_ENET_HW_H__ */
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