262 lines
9.7 KiB
C
262 lines
9.7 KiB
C
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/*
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* Driver for the Conexant CX25821 PCIe bridge
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*
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* Copyright (C) 2009 Conexant Systems Inc.
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* Authors <shu.lin@conexant.com>, <hiep.huynh@conexant.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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*
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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*/
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#ifndef __ATHENA_SRAM_H__
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#define __ATHENA_SRAM_H__
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/* #define RX_SRAM_START_SIZE = 0; // Start of reserved SRAM */
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#define VID_CMDS_SIZE 80 /* Video CMDS size in bytes */
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#define AUDIO_CMDS_SIZE 80 /* AUDIO CMDS size in bytes */
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#define MBIF_CMDS_SIZE 80 /* MBIF CMDS size in bytes */
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/* #define RX_SRAM_POOL_START_SIZE = 0; // Start of useable RX SRAM for buffers */
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#define VID_IQ_SIZE 64 /* VID instruction queue size in bytes */
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#define MBIF_IQ_SIZE 64
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#define AUDIO_IQ_SIZE 64 /* AUD instruction queue size in bytes */
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#define VID_CDT_SIZE 64 /* VID cluster descriptor table size in bytes */
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#define MBIF_CDT_SIZE 64 /* MBIF/HBI cluster descriptor table size in bytes */
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#define AUDIO_CDT_SIZE 48 /* AUD cluster descriptor table size in bytes */
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/* #define RX_SRAM_POOL_FREE_SIZE = 16; // Start of available RX SRAM */
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/* #define RX_SRAM_END_SIZE = 0; // End of RX SRAM */
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/* #define TX_SRAM_POOL_START_SIZE = 0; // Start of transmit pool SRAM */
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/* #define MSI_DATA_SIZE = 64; // Reserved (MSI Data, RISC working stora */
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#define VID_CLUSTER_SIZE 1440 /* VID cluster data line */
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#define AUDIO_CLUSTER_SIZE 128 /* AUDIO cluster data line */
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#define MBIF_CLUSTER_SIZE 1440 /* MBIF/HBI cluster data line */
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/* #define TX_SRAM_POOL_FREE_SIZE = 704; // Start of available TX SRAM */
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/* #define TX_SRAM_END_SIZE = 0; // End of TX SRAM */
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/* Receive SRAM */
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#define RX_SRAM_START 0x10000
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#define VID_A_DOWN_CMDS 0x10000
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#define VID_B_DOWN_CMDS 0x10050
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#define VID_C_DOWN_CMDS 0x100A0
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#define VID_D_DOWN_CMDS 0x100F0
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#define VID_E_DOWN_CMDS 0x10140
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#define VID_F_DOWN_CMDS 0x10190
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#define VID_G_DOWN_CMDS 0x101E0
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#define VID_H_DOWN_CMDS 0x10230
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#define VID_A_UP_CMDS 0x10280
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#define VID_B_UP_CMDS 0x102D0
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#define VID_C_UP_CMDS 0x10320
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#define VID_D_UP_CMDS 0x10370
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#define VID_E_UP_CMDS 0x103C0
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#define VID_F_UP_CMDS 0x10410
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#define VID_I_UP_CMDS 0x10460
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#define VID_J_UP_CMDS 0x104B0
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#define AUD_A_DOWN_CMDS 0x10500
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#define AUD_B_DOWN_CMDS 0x10550
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#define AUD_C_DOWN_CMDS 0x105A0
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#define AUD_D_DOWN_CMDS 0x105F0
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#define AUD_A_UP_CMDS 0x10640
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#define AUD_B_UP_CMDS 0x10690
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#define AUD_C_UP_CMDS 0x106E0
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#define AUD_E_UP_CMDS 0x10730
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#define MBIF_A_DOWN_CMDS 0x10780
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#define MBIF_B_DOWN_CMDS 0x107D0
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#define DMA_SCRATCH_PAD 0x10820 /* Scratch pad area from 0x10820 to 0x10B40 */
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/* #define RX_SRAM_POOL_START = 0x105B0; */
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#define VID_A_IQ 0x11000
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#define VID_B_IQ 0x11040
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#define VID_C_IQ 0x11080
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#define VID_D_IQ 0x110C0
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#define VID_E_IQ 0x11100
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#define VID_F_IQ 0x11140
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#define VID_G_IQ 0x11180
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#define VID_H_IQ 0x111C0
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#define VID_I_IQ 0x11200
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#define VID_J_IQ 0x11240
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#define AUD_A_IQ 0x11280
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#define AUD_B_IQ 0x112C0
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#define AUD_C_IQ 0x11300
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#define AUD_D_IQ 0x11340
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#define AUD_E_IQ 0x11380
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#define MBIF_A_IQ 0x11000
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#define MBIF_B_IQ 0x110C0
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#define VID_A_CDT 0x10C00
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#define VID_B_CDT 0x10C40
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#define VID_C_CDT 0x10C80
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#define VID_D_CDT 0x10CC0
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#define VID_E_CDT 0x10D00
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#define VID_F_CDT 0x10D40
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#define VID_G_CDT 0x10D80
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#define VID_H_CDT 0x10DC0
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#define VID_I_CDT 0x10E00
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#define VID_J_CDT 0x10E40
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#define AUD_A_CDT 0x10E80
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#define AUD_B_CDT 0x10EB0
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#define AUD_C_CDT 0x10EE0
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#define AUD_D_CDT 0x10F10
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#define AUD_E_CDT 0x10F40
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#define MBIF_A_CDT 0x10C00
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#define MBIF_B_CDT 0x10CC0
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/* Cluster Buffer for RX */
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#define VID_A_UP_CLUSTER_1 0x11400
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#define VID_A_UP_CLUSTER_2 0x119A0
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#define VID_A_UP_CLUSTER_3 0x11F40
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#define VID_A_UP_CLUSTER_4 0x124E0
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#define VID_B_UP_CLUSTER_1 0x12A80
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#define VID_B_UP_CLUSTER_2 0x13020
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#define VID_B_UP_CLUSTER_3 0x135C0
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#define VID_B_UP_CLUSTER_4 0x13B60
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#define VID_C_UP_CLUSTER_1 0x14100
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#define VID_C_UP_CLUSTER_2 0x146A0
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#define VID_C_UP_CLUSTER_3 0x14C40
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#define VID_C_UP_CLUSTER_4 0x151E0
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#define VID_D_UP_CLUSTER_1 0x15780
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#define VID_D_UP_CLUSTER_2 0x15D20
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#define VID_D_UP_CLUSTER_3 0x162C0
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#define VID_D_UP_CLUSTER_4 0x16860
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#define VID_E_UP_CLUSTER_1 0x16E00
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#define VID_E_UP_CLUSTER_2 0x173A0
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#define VID_E_UP_CLUSTER_3 0x17940
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#define VID_E_UP_CLUSTER_4 0x17EE0
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#define VID_F_UP_CLUSTER_1 0x18480
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#define VID_F_UP_CLUSTER_2 0x18A20
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#define VID_F_UP_CLUSTER_3 0x18FC0
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#define VID_F_UP_CLUSTER_4 0x19560
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#define VID_I_UP_CLUSTER_1 0x19B00
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#define VID_I_UP_CLUSTER_2 0x1A0A0
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#define VID_I_UP_CLUSTER_3 0x1A640
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#define VID_I_UP_CLUSTER_4 0x1ABE0
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#define VID_J_UP_CLUSTER_1 0x1B180
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#define VID_J_UP_CLUSTER_2 0x1B720
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#define VID_J_UP_CLUSTER_3 0x1BCC0
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#define VID_J_UP_CLUSTER_4 0x1C260
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#define AUD_A_UP_CLUSTER_1 0x1C800
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#define AUD_A_UP_CLUSTER_2 0x1C880
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#define AUD_A_UP_CLUSTER_3 0x1C900
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#define AUD_B_UP_CLUSTER_1 0x1C980
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#define AUD_B_UP_CLUSTER_2 0x1CA00
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#define AUD_B_UP_CLUSTER_3 0x1CA80
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#define AUD_C_UP_CLUSTER_1 0x1CB00
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#define AUD_C_UP_CLUSTER_2 0x1CB80
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#define AUD_C_UP_CLUSTER_3 0x1CC00
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#define AUD_E_UP_CLUSTER_1 0x1CC80
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#define AUD_E_UP_CLUSTER_2 0x1CD00
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#define AUD_E_UP_CLUSTER_3 0x1CD80
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#define RX_SRAM_POOL_FREE 0x1CE00
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#define RX_SRAM_END 0x1D000
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/* Free Receive SRAM 144 Bytes */
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/* Transmit SRAM */
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#define TX_SRAM_POOL_START 0x00000
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#define VID_A_DOWN_CLUSTER_1 0x00040
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#define VID_A_DOWN_CLUSTER_2 0x005E0
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#define VID_A_DOWN_CLUSTER_3 0x00B80
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#define VID_A_DOWN_CLUSTER_4 0x01120
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#define VID_B_DOWN_CLUSTER_1 0x016C0
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#define VID_B_DOWN_CLUSTER_2 0x01C60
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#define VID_B_DOWN_CLUSTER_3 0x02200
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#define VID_B_DOWN_CLUSTER_4 0x027A0
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#define VID_C_DOWN_CLUSTER_1 0x02D40
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#define VID_C_DOWN_CLUSTER_2 0x032E0
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#define VID_C_DOWN_CLUSTER_3 0x03880
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#define VID_C_DOWN_CLUSTER_4 0x03E20
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#define VID_D_DOWN_CLUSTER_1 0x043C0
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#define VID_D_DOWN_CLUSTER_2 0x04960
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#define VID_D_DOWN_CLUSTER_3 0x04F00
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#define VID_D_DOWN_CLUSTER_4 0x054A0
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#define VID_E_DOWN_CLUSTER_1 0x05a40
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#define VID_E_DOWN_CLUSTER_2 0x05FE0
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#define VID_E_DOWN_CLUSTER_3 0x06580
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#define VID_E_DOWN_CLUSTER_4 0x06B20
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#define VID_F_DOWN_CLUSTER_1 0x070C0
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#define VID_F_DOWN_CLUSTER_2 0x07660
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#define VID_F_DOWN_CLUSTER_3 0x07C00
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#define VID_F_DOWN_CLUSTER_4 0x081A0
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#define VID_G_DOWN_CLUSTER_1 0x08740
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#define VID_G_DOWN_CLUSTER_2 0x08CE0
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#define VID_G_DOWN_CLUSTER_3 0x09280
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#define VID_G_DOWN_CLUSTER_4 0x09820
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#define VID_H_DOWN_CLUSTER_1 0x09DC0
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#define VID_H_DOWN_CLUSTER_2 0x0A360
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#define VID_H_DOWN_CLUSTER_3 0x0A900
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#define VID_H_DOWN_CLUSTER_4 0x0AEA0
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#define AUD_A_DOWN_CLUSTER_1 0x0B500
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#define AUD_A_DOWN_CLUSTER_2 0x0B580
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#define AUD_A_DOWN_CLUSTER_3 0x0B600
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#define AUD_B_DOWN_CLUSTER_1 0x0B680
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#define AUD_B_DOWN_CLUSTER_2 0x0B700
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#define AUD_B_DOWN_CLUSTER_3 0x0B780
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#define AUD_C_DOWN_CLUSTER_1 0x0B800
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#define AUD_C_DOWN_CLUSTER_2 0x0B880
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#define AUD_C_DOWN_CLUSTER_3 0x0B900
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#define AUD_D_DOWN_CLUSTER_1 0x0B980
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#define AUD_D_DOWN_CLUSTER_2 0x0BA00
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#define AUD_D_DOWN_CLUSTER_3 0x0BA80
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#define TX_SRAM_POOL_FREE 0x0BB00
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#define TX_SRAM_END 0x0C000
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#define BYTES_TO_DWORDS(bcount) ((bcount) >> 2)
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#define BYTES_TO_QWORDS(bcount) ((bcount) >> 3)
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#define BYTES_TO_OWORDS(bcount) ((bcount) >> 4)
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#define VID_IQ_SIZE_DW BYTES_TO_DWORDS(VID_IQ_SIZE)
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#define VID_CDT_SIZE_QW BYTES_TO_QWORDS(VID_CDT_SIZE)
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#define VID_CLUSTER_SIZE_OW BYTES_TO_OWORDS(VID_CLUSTER_SIZE)
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#define AUDIO_IQ_SIZE_DW BYTES_TO_DWORDS(AUDIO_IQ_SIZE)
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#define AUDIO_CDT_SIZE_QW BYTES_TO_QWORDS(AUDIO_CDT_SIZE)
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#define AUDIO_CLUSTER_SIZE_QW BYTES_TO_QWORDS(AUDIO_CLUSTER_SIZE)
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#define MBIF_IQ_SIZE_DW BYTES_TO_DWORDS(MBIF_IQ_SIZE)
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#define MBIF_CDT_SIZE_QW BYTES_TO_QWORDS(MBIF_CDT_SIZE)
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#define MBIF_CLUSTER_SIZE_OW BYTES_TO_OWORDS(MBIF_CLUSTER_SIZE)
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#endif
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