511 lines
15 KiB
C
511 lines
15 KiB
C
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/*
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*
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Copyright (c) Eicon Networks, 2002.
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*
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This source file is supplied for the use with
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Eicon Networks range of DIVA Server Adapters.
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*
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Eicon File Revision : 2.1
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*
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2, or (at your option)
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any later version.
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*
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY OF ANY KIND WHATSOEVER INCLUDING ANY
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implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
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See the GNU General Public License for more details.
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*
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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*
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*/
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#include "platform.h"
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#include "di_defs.h"
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#include "pc.h"
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#include "pr_pc.h"
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#include "di.h"
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#include "mi_pc.h"
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#include "pc_maint.h"
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#include "divasync.h"
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#include "pc_init.h"
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#include "io.h"
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#include "helpers.h"
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#include "dsrv4bri.h"
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#include "dsp_defs.h"
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#include "sdp_hdr.h"
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/*****************************************************************************/
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#define MAX_XLOG_SIZE (64 * 1024)
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/* --------------------------------------------------------------------------
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Recovery XLOG from QBRI Card
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-------------------------------------------------------------------------- */
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static void qBri_cpu_trapped(PISDN_ADAPTER IoAdapter) {
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byte __iomem *base;
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word *Xlog;
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dword regs[4], TrapID, offset, size;
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Xdesc xlogDesc;
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int factor = (IoAdapter->tasks == 1) ? 1 : 2;
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/*
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* check for trapped MIPS 46xx CPU, dump exception frame
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*/
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base = DIVA_OS_MEM_ATTACH_CONTROL(IoAdapter);
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offset = IoAdapter->ControllerNumber * (IoAdapter->MemorySize >> factor);
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TrapID = READ_DWORD(&base[0x80]);
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if ((TrapID == 0x99999999) || (TrapID == 0x99999901))
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{
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dump_trap_frame(IoAdapter, &base[0x90]);
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IoAdapter->trapped = 1;
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}
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regs[0] = READ_DWORD((base + offset) + 0x70);
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regs[1] = READ_DWORD((base + offset) + 0x74);
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regs[2] = READ_DWORD((base + offset) + 0x78);
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regs[3] = READ_DWORD((base + offset) + 0x7c);
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regs[0] &= IoAdapter->MemorySize - 1;
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if ((regs[0] >= offset)
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&& (regs[0] < offset + (IoAdapter->MemorySize >> factor) - 1))
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{
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if (!(Xlog = (word *)diva_os_malloc(0, MAX_XLOG_SIZE))) {
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DIVA_OS_MEM_DETACH_CONTROL(IoAdapter, base);
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return;
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}
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size = offset + (IoAdapter->MemorySize >> factor) - regs[0];
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if (size > MAX_XLOG_SIZE)
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size = MAX_XLOG_SIZE;
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memcpy_fromio(Xlog, &base[regs[0]], size);
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xlogDesc.buf = Xlog;
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xlogDesc.cnt = READ_WORD(&base[regs[1] & (IoAdapter->MemorySize - 1)]);
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xlogDesc.out = READ_WORD(&base[regs[2] & (IoAdapter->MemorySize - 1)]);
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dump_xlog_buffer(IoAdapter, &xlogDesc);
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diva_os_free(0, Xlog);
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IoAdapter->trapped = 2;
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}
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DIVA_OS_MEM_DETACH_CONTROL(IoAdapter, base);
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}
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/* --------------------------------------------------------------------------
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Reset QBRI Hardware
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-------------------------------------------------------------------------- */
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static void reset_qBri_hardware(PISDN_ADAPTER IoAdapter) {
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word volatile __iomem *qBriReset;
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byte volatile __iomem *qBriCntrl;
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byte volatile __iomem *p;
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qBriReset = (word volatile __iomem *)DIVA_OS_MEM_ATTACH_PROM(IoAdapter);
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WRITE_WORD(qBriReset, READ_WORD(qBriReset) | PLX9054_SOFT_RESET);
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diva_os_wait(1);
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WRITE_WORD(qBriReset, READ_WORD(qBriReset) & ~PLX9054_SOFT_RESET);
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diva_os_wait(1);
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WRITE_WORD(qBriReset, READ_WORD(qBriReset) | PLX9054_RELOAD_EEPROM);
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diva_os_wait(1);
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WRITE_WORD(qBriReset, READ_WORD(qBriReset) & ~PLX9054_RELOAD_EEPROM);
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diva_os_wait(1);
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DIVA_OS_MEM_DETACH_PROM(IoAdapter, qBriReset);
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qBriCntrl = DIVA_OS_MEM_ATTACH_CTLREG(IoAdapter);
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p = &qBriCntrl[DIVA_4BRI_REVISION(IoAdapter) ? (MQ2_BREG_RISC) : (MQ_BREG_RISC)];
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WRITE_DWORD(p, 0);
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DIVA_OS_MEM_DETACH_CTLREG(IoAdapter, qBriCntrl);
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DBG_TRC(("resetted board @ reset addr 0x%08lx", qBriReset))
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DBG_TRC(("resetted board @ cntrl addr 0x%08lx", p))
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}
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/* --------------------------------------------------------------------------
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Start Card CPU
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-------------------------------------------------------------------------- */
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void start_qBri_hardware(PISDN_ADAPTER IoAdapter) {
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byte volatile __iomem *qBriReset;
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byte volatile __iomem *p;
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p = DIVA_OS_MEM_ATTACH_CTLREG(IoAdapter);
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qBriReset = &p[(DIVA_4BRI_REVISION(IoAdapter)) ? (MQ2_BREG_RISC) : (MQ_BREG_RISC)];
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WRITE_DWORD(qBriReset, MQ_RISC_COLD_RESET_MASK);
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diva_os_wait(2);
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WRITE_DWORD(qBriReset, MQ_RISC_WARM_RESET_MASK | MQ_RISC_COLD_RESET_MASK);
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diva_os_wait(10);
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DIVA_OS_MEM_DETACH_CTLREG(IoAdapter, p);
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DBG_TRC(("started processor @ addr 0x%08lx", qBriReset))
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}
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/* --------------------------------------------------------------------------
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Stop Card CPU
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-------------------------------------------------------------------------- */
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static void stop_qBri_hardware(PISDN_ADAPTER IoAdapter) {
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byte volatile __iomem *p;
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dword volatile __iomem *qBriReset;
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dword volatile __iomem *qBriIrq;
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dword volatile __iomem *qBriIsacDspReset;
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int rev2 = DIVA_4BRI_REVISION(IoAdapter);
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int reset_offset = rev2 ? (MQ2_BREG_RISC) : (MQ_BREG_RISC);
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int irq_offset = rev2 ? (MQ2_BREG_IRQ_TEST) : (MQ_BREG_IRQ_TEST);
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int hw_offset = rev2 ? (MQ2_ISAC_DSP_RESET) : (MQ_ISAC_DSP_RESET);
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if (IoAdapter->ControllerNumber > 0)
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return;
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p = DIVA_OS_MEM_ATTACH_CTLREG(IoAdapter);
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qBriReset = (dword volatile __iomem *)&p[reset_offset];
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qBriIsacDspReset = (dword volatile __iomem *)&p[hw_offset];
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/*
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* clear interrupt line (reset Local Interrupt Test Register)
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*/
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WRITE_DWORD(qBriReset, 0);
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WRITE_DWORD(qBriIsacDspReset, 0);
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DIVA_OS_MEM_DETACH_CTLREG(IoAdapter, p);
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p = DIVA_OS_MEM_ATTACH_RESET(IoAdapter);
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WRITE_BYTE(&p[PLX9054_INTCSR], 0x00); /* disable PCI interrupts */
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DIVA_OS_MEM_DETACH_RESET(IoAdapter, p);
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p = DIVA_OS_MEM_ATTACH_CTLREG(IoAdapter);
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qBriIrq = (dword volatile __iomem *)&p[irq_offset];
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WRITE_DWORD(qBriIrq, MQ_IRQ_REQ_OFF);
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DIVA_OS_MEM_DETACH_CTLREG(IoAdapter, p);
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DBG_TRC(("stopped processor @ addr 0x%08lx", qBriReset))
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}
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/* --------------------------------------------------------------------------
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FPGA download
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-------------------------------------------------------------------------- */
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#define FPGA_NAME_OFFSET 0x10
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static byte *qBri_check_FPGAsrc(PISDN_ADAPTER IoAdapter, char *FileName,
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dword *Length, dword *code) {
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byte *File;
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char *fpgaFile, *fpgaType, *fpgaDate, *fpgaTime;
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dword fpgaFlen, fpgaTlen, fpgaDlen, cnt, year, i;
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if (!(File = (byte *)xdiLoadFile(FileName, Length, 0))) {
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return (NULL);
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}
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/*
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* scan file until FF and put id string into buffer
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*/
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for (i = 0; File[i] != 0xff;)
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{
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if (++i >= *Length)
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{
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DBG_FTL(("FPGA download: start of data header not found"))
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xdiFreeFile(File);
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return (NULL);
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}
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}
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*code = i++;
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if ((File[i] & 0xF0) != 0x20)
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{
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DBG_FTL(("FPGA download: data header corrupted"))
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xdiFreeFile(File);
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return (NULL);
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}
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fpgaFlen = (dword)File[FPGA_NAME_OFFSET - 1];
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if (fpgaFlen == 0)
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fpgaFlen = 12;
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fpgaFile = (char *)&File[FPGA_NAME_OFFSET];
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fpgaTlen = (dword)fpgaFile[fpgaFlen + 2];
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if (fpgaTlen == 0)
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fpgaTlen = 10;
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fpgaType = (char *)&fpgaFile[fpgaFlen + 3];
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fpgaDlen = (dword) fpgaType[fpgaTlen + 2];
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if (fpgaDlen == 0)
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fpgaDlen = 11;
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fpgaDate = (char *)&fpgaType[fpgaTlen + 3];
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fpgaTime = (char *)&fpgaDate[fpgaDlen + 3];
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cnt = (dword)(((File[i] & 0x0F) << 20) + (File[i + 1] << 12)
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+ (File[i + 2] << 4) + (File[i + 3] >> 4));
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if ((dword)(i + (cnt / 8)) > *Length)
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{
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DBG_FTL(("FPGA download: '%s' file too small (%ld < %ld)",
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FileName, *Length, code + ((cnt + 7) / 8)))
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xdiFreeFile(File);
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return (NULL);
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}
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i = 0;
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do
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{
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while ((fpgaDate[i] != '\0')
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&& ((fpgaDate[i] < '0') || (fpgaDate[i] > '9')))
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{
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i++;
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}
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year = 0;
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while ((fpgaDate[i] >= '0') && (fpgaDate[i] <= '9'))
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year = year * 10 + (fpgaDate[i++] - '0');
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} while ((year < 2000) && (fpgaDate[i] != '\0'));
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switch (IoAdapter->cardType) {
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case CARDTYPE_DIVASRV_B_2F_PCI:
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break;
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default:
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if (year >= 2001) {
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IoAdapter->fpga_features |= PCINIT_FPGA_PLX_ACCESS_SUPPORTED;
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}
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}
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DBG_LOG(("FPGA[%s] file %s (%s %s) len %d",
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fpgaType, fpgaFile, fpgaDate, fpgaTime, cnt))
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return (File);
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}
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/******************************************************************************/
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#define FPGA_PROG 0x0001 /* PROG enable low */
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#define FPGA_BUSY 0x0002 /* BUSY high, DONE low */
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#define FPGA_CS 0x000C /* Enable I/O pins */
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#define FPGA_CCLK 0x0100
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#define FPGA_DOUT 0x0400
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#define FPGA_DIN FPGA_DOUT /* bidirectional I/O */
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int qBri_FPGA_download(PISDN_ADAPTER IoAdapter) {
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int bit;
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byte *File;
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dword code, FileLength;
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word volatile __iomem *addr = (word volatile __iomem *)DIVA_OS_MEM_ATTACH_PROM(IoAdapter);
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word val, baseval = FPGA_CS | FPGA_PROG;
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if (DIVA_4BRI_REVISION(IoAdapter))
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{
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char *name;
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switch (IoAdapter->cardType) {
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case CARDTYPE_DIVASRV_B_2F_PCI:
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name = "dsbri2f.bit";
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break;
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case CARDTYPE_DIVASRV_B_2M_V2_PCI:
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case CARDTYPE_DIVASRV_VOICE_B_2M_V2_PCI:
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name = "dsbri2m.bit";
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break;
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default:
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name = "ds4bri2.bit";
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}
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File = qBri_check_FPGAsrc(IoAdapter, name,
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&FileLength, &code);
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}
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else
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{
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File = qBri_check_FPGAsrc(IoAdapter, "ds4bri.bit",
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&FileLength, &code);
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}
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if (!File) {
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DIVA_OS_MEM_DETACH_PROM(IoAdapter, addr);
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return (0);
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}
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/*
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* prepare download, pulse PROGRAM pin down.
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*/
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WRITE_WORD(addr, baseval & ~FPGA_PROG); /* PROGRAM low pulse */
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WRITE_WORD(addr, baseval); /* release */
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diva_os_wait(50); /* wait until FPGA finished internal memory clear */
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/*
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* check done pin, must be low
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*/
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if (READ_WORD(addr) & FPGA_BUSY)
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{
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DBG_FTL(("FPGA download: acknowledge for FPGA memory clear missing"))
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xdiFreeFile(File);
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DIVA_OS_MEM_DETACH_PROM(IoAdapter, addr);
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return (0);
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}
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/*
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* put data onto the FPGA
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*/
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while (code < FileLength)
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{
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val = ((word)File[code++]) << 3;
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for (bit = 8; bit-- > 0; val <<= 1) /* put byte onto FPGA */
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{
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baseval &= ~FPGA_DOUT; /* clr data bit */
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baseval |= (val & FPGA_DOUT); /* copy data bit */
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WRITE_WORD(addr, baseval);
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WRITE_WORD(addr, baseval | FPGA_CCLK); /* set CCLK hi */
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WRITE_WORD(addr, baseval | FPGA_CCLK); /* set CCLK hi */
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WRITE_WORD(addr, baseval); /* set CCLK lo */
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}
|
||
|
|
}
|
||
|
|
xdiFreeFile(File);
|
||
|
|
diva_os_wait(100);
|
||
|
|
val = READ_WORD(addr);
|
||
|
|
|
||
|
|
DIVA_OS_MEM_DETACH_PROM(IoAdapter, addr);
|
||
|
|
|
||
|
|
if (!(val & FPGA_BUSY))
|
||
|
|
{
|
||
|
|
DBG_FTL(("FPGA download: chip remains in busy state (0x%04x)", val))
|
||
|
|
return (0);
|
||
|
|
}
|
||
|
|
|
||
|
|
return (1);
|
||
|
|
}
|
||
|
|
|
||
|
|
static int load_qBri_hardware(PISDN_ADAPTER IoAdapter) {
|
||
|
|
return (0);
|
||
|
|
}
|
||
|
|
|
||
|
|
/* --------------------------------------------------------------------------
|
||
|
|
Card ISR
|
||
|
|
-------------------------------------------------------------------------- */
|
||
|
|
static int qBri_ISR(struct _ISDN_ADAPTER *IoAdapter) {
|
||
|
|
dword volatile __iomem *qBriIrq;
|
||
|
|
|
||
|
|
PADAPTER_LIST_ENTRY QuadroList = IoAdapter->QuadroList;
|
||
|
|
|
||
|
|
word i;
|
||
|
|
int serviced = 0;
|
||
|
|
byte __iomem *p;
|
||
|
|
|
||
|
|
p = DIVA_OS_MEM_ATTACH_RESET(IoAdapter);
|
||
|
|
|
||
|
|
if (!(READ_BYTE(&p[PLX9054_INTCSR]) & 0x80)) {
|
||
|
|
DIVA_OS_MEM_DETACH_RESET(IoAdapter, p);
|
||
|
|
return (0);
|
||
|
|
}
|
||
|
|
DIVA_OS_MEM_DETACH_RESET(IoAdapter, p);
|
||
|
|
|
||
|
|
/*
|
||
|
|
* clear interrupt line (reset Local Interrupt Test Register)
|
||
|
|
*/
|
||
|
|
p = DIVA_OS_MEM_ATTACH_CTLREG(IoAdapter);
|
||
|
|
qBriIrq = (dword volatile __iomem *)(&p[DIVA_4BRI_REVISION(IoAdapter) ? (MQ2_BREG_IRQ_TEST) : (MQ_BREG_IRQ_TEST)]);
|
||
|
|
WRITE_DWORD(qBriIrq, MQ_IRQ_REQ_OFF);
|
||
|
|
DIVA_OS_MEM_DETACH_CTLREG(IoAdapter, p);
|
||
|
|
|
||
|
|
for (i = 0; i < IoAdapter->tasks; ++i)
|
||
|
|
{
|
||
|
|
IoAdapter = QuadroList->QuadroAdapter[i];
|
||
|
|
|
||
|
|
if (IoAdapter && IoAdapter->Initialized
|
||
|
|
&& IoAdapter->tst_irq(&IoAdapter->a))
|
||
|
|
{
|
||
|
|
IoAdapter->IrqCount++;
|
||
|
|
serviced = 1;
|
||
|
|
diva_os_schedule_soft_isr(&IoAdapter->isr_soft_isr);
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
return (serviced);
|
||
|
|
}
|
||
|
|
|
||
|
|
/* --------------------------------------------------------------------------
|
||
|
|
Does disable the interrupt on the card
|
||
|
|
-------------------------------------------------------------------------- */
|
||
|
|
static void disable_qBri_interrupt(PISDN_ADAPTER IoAdapter) {
|
||
|
|
dword volatile __iomem *qBriIrq;
|
||
|
|
byte __iomem *p;
|
||
|
|
|
||
|
|
if (IoAdapter->ControllerNumber > 0)
|
||
|
|
return;
|
||
|
|
/*
|
||
|
|
* clear interrupt line (reset Local Interrupt Test Register)
|
||
|
|
*/
|
||
|
|
p = DIVA_OS_MEM_ATTACH_RESET(IoAdapter);
|
||
|
|
WRITE_BYTE(&p[PLX9054_INTCSR], 0x00); /* disable PCI interrupts */
|
||
|
|
DIVA_OS_MEM_DETACH_RESET(IoAdapter, p);
|
||
|
|
|
||
|
|
p = DIVA_OS_MEM_ATTACH_CTLREG(IoAdapter);
|
||
|
|
qBriIrq = (dword volatile __iomem *)(&p[DIVA_4BRI_REVISION(IoAdapter) ? (MQ2_BREG_IRQ_TEST) : (MQ_BREG_IRQ_TEST)]);
|
||
|
|
WRITE_DWORD(qBriIrq, MQ_IRQ_REQ_OFF);
|
||
|
|
DIVA_OS_MEM_DETACH_CTLREG(IoAdapter, p);
|
||
|
|
}
|
||
|
|
|
||
|
|
/* --------------------------------------------------------------------------
|
||
|
|
Install Adapter Entry Points
|
||
|
|
-------------------------------------------------------------------------- */
|
||
|
|
static void set_common_qBri_functions(PISDN_ADAPTER IoAdapter) {
|
||
|
|
ADAPTER *a;
|
||
|
|
|
||
|
|
a = &IoAdapter->a;
|
||
|
|
|
||
|
|
a->ram_in = mem_in;
|
||
|
|
a->ram_inw = mem_inw;
|
||
|
|
a->ram_in_buffer = mem_in_buffer;
|
||
|
|
a->ram_look_ahead = mem_look_ahead;
|
||
|
|
a->ram_out = mem_out;
|
||
|
|
a->ram_outw = mem_outw;
|
||
|
|
a->ram_out_buffer = mem_out_buffer;
|
||
|
|
a->ram_inc = mem_inc;
|
||
|
|
|
||
|
|
IoAdapter->out = pr_out;
|
||
|
|
IoAdapter->dpc = pr_dpc;
|
||
|
|
IoAdapter->tst_irq = scom_test_int;
|
||
|
|
IoAdapter->clr_irq = scom_clear_int;
|
||
|
|
IoAdapter->pcm = (struct pc_maint *)MIPS_MAINT_OFFS;
|
||
|
|
|
||
|
|
IoAdapter->load = load_qBri_hardware;
|
||
|
|
|
||
|
|
IoAdapter->disIrq = disable_qBri_interrupt;
|
||
|
|
IoAdapter->rstFnc = reset_qBri_hardware;
|
||
|
|
IoAdapter->stop = stop_qBri_hardware;
|
||
|
|
IoAdapter->trapFnc = qBri_cpu_trapped;
|
||
|
|
|
||
|
|
IoAdapter->diva_isr_handler = qBri_ISR;
|
||
|
|
|
||
|
|
IoAdapter->a.io = (void *)IoAdapter;
|
||
|
|
}
|
||
|
|
|
||
|
|
static void set_qBri_functions(PISDN_ADAPTER IoAdapter) {
|
||
|
|
if (!IoAdapter->tasks) {
|
||
|
|
IoAdapter->tasks = MQ_INSTANCE_COUNT;
|
||
|
|
}
|
||
|
|
IoAdapter->MemorySize = MQ_MEMORY_SIZE;
|
||
|
|
set_common_qBri_functions(IoAdapter);
|
||
|
|
diva_os_set_qBri_functions(IoAdapter);
|
||
|
|
}
|
||
|
|
|
||
|
|
static void set_qBri2_functions(PISDN_ADAPTER IoAdapter) {
|
||
|
|
if (!IoAdapter->tasks) {
|
||
|
|
IoAdapter->tasks = MQ_INSTANCE_COUNT;
|
||
|
|
}
|
||
|
|
IoAdapter->MemorySize = (IoAdapter->tasks == 1) ? BRI2_MEMORY_SIZE : MQ2_MEMORY_SIZE;
|
||
|
|
set_common_qBri_functions(IoAdapter);
|
||
|
|
diva_os_set_qBri2_functions(IoAdapter);
|
||
|
|
}
|
||
|
|
|
||
|
|
/******************************************************************************/
|
||
|
|
|
||
|
|
void prepare_qBri_functions(PISDN_ADAPTER IoAdapter) {
|
||
|
|
|
||
|
|
set_qBri_functions(IoAdapter->QuadroList->QuadroAdapter[0]);
|
||
|
|
set_qBri_functions(IoAdapter->QuadroList->QuadroAdapter[1]);
|
||
|
|
set_qBri_functions(IoAdapter->QuadroList->QuadroAdapter[2]);
|
||
|
|
set_qBri_functions(IoAdapter->QuadroList->QuadroAdapter[3]);
|
||
|
|
|
||
|
|
}
|
||
|
|
|
||
|
|
void prepare_qBri2_functions(PISDN_ADAPTER IoAdapter) {
|
||
|
|
if (!IoAdapter->tasks) {
|
||
|
|
IoAdapter->tasks = MQ_INSTANCE_COUNT;
|
||
|
|
}
|
||
|
|
|
||
|
|
set_qBri2_functions(IoAdapter->QuadroList->QuadroAdapter[0]);
|
||
|
|
if (IoAdapter->tasks > 1) {
|
||
|
|
set_qBri2_functions(IoAdapter->QuadroList->QuadroAdapter[1]);
|
||
|
|
set_qBri2_functions(IoAdapter->QuadroList->QuadroAdapter[2]);
|
||
|
|
set_qBri2_functions(IoAdapter->QuadroList->QuadroAdapter[3]);
|
||
|
|
}
|
||
|
|
|
||
|
|
}
|
||
|
|
|
||
|
|
/* -------------------------------------------------------------------------- */
|