285 lines
8.4 KiB
C
285 lines
8.4 KiB
C
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/*
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* Copyright 2013 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: Alex Deucher
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*/
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#include <drm/drmP.h>
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#include "radeon.h"
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#include "radeon_asic.h"
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#include "radeon_trace.h"
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#include "sid.h"
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u32 si_gpu_check_soft_reset(struct radeon_device *rdev);
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/**
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* si_dma_is_lockup - Check if the DMA engine is locked up
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*
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* @rdev: radeon_device pointer
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* @ring: radeon_ring structure holding ring information
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*
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* Check if the async DMA engine is locked up.
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* Returns true if the engine appears to be locked up, false if not.
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*/
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bool si_dma_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring)
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{
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u32 reset_mask = si_gpu_check_soft_reset(rdev);
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u32 mask;
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if (ring->idx == R600_RING_TYPE_DMA_INDEX)
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mask = RADEON_RESET_DMA;
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else
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mask = RADEON_RESET_DMA1;
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if (!(reset_mask & mask)) {
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radeon_ring_lockup_update(rdev, ring);
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return false;
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}
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return radeon_ring_test_lockup(rdev, ring);
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}
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/**
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* si_dma_vm_copy_pages - update PTEs by copying them from the GART
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*
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* @rdev: radeon_device pointer
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* @ib: indirect buffer to fill with commands
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* @pe: addr of the page entry
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* @src: src addr where to copy from
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* @count: number of page entries to update
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*
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* Update PTEs by copying them from the GART using the DMA (SI).
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*/
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void si_dma_vm_copy_pages(struct radeon_device *rdev,
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struct radeon_ib *ib,
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uint64_t pe, uint64_t src,
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unsigned count)
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{
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while (count) {
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unsigned bytes = count * 8;
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if (bytes > 0xFFFF8)
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bytes = 0xFFFF8;
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ib->ptr[ib->length_dw++] = DMA_PACKET(DMA_PACKET_COPY,
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1, 0, 0, bytes);
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ib->ptr[ib->length_dw++] = lower_32_bits(pe);
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ib->ptr[ib->length_dw++] = lower_32_bits(src);
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ib->ptr[ib->length_dw++] = upper_32_bits(pe) & 0xff;
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ib->ptr[ib->length_dw++] = upper_32_bits(src) & 0xff;
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pe += bytes;
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src += bytes;
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count -= bytes / 8;
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}
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}
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/**
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* si_dma_vm_write_pages - update PTEs by writing them manually
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*
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* @rdev: radeon_device pointer
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* @ib: indirect buffer to fill with commands
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* @pe: addr of the page entry
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* @addr: dst addr to write into pe
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* @count: number of page entries to update
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* @incr: increase next addr by incr bytes
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* @flags: access flags
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*
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* Update PTEs by writing them manually using the DMA (SI).
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*/
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void si_dma_vm_write_pages(struct radeon_device *rdev,
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struct radeon_ib *ib,
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uint64_t pe,
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uint64_t addr, unsigned count,
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uint32_t incr, uint32_t flags)
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{
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uint64_t value;
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unsigned ndw;
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while (count) {
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ndw = count * 2;
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if (ndw > 0xFFFFE)
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ndw = 0xFFFFE;
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/* for non-physically contiguous pages (system) */
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ib->ptr[ib->length_dw++] = DMA_PACKET(DMA_PACKET_WRITE, 0, 0, 0, ndw);
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ib->ptr[ib->length_dw++] = pe;
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ib->ptr[ib->length_dw++] = upper_32_bits(pe) & 0xff;
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for (; ndw > 0; ndw -= 2, --count, pe += 8) {
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if (flags & R600_PTE_SYSTEM) {
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value = radeon_vm_map_gart(rdev, addr);
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value &= 0xFFFFFFFFFFFFF000ULL;
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} else if (flags & R600_PTE_VALID) {
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value = addr;
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} else {
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value = 0;
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}
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addr += incr;
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value |= flags;
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ib->ptr[ib->length_dw++] = value;
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ib->ptr[ib->length_dw++] = upper_32_bits(value);
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}
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}
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}
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/**
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* si_dma_vm_set_pages - update the page tables using the DMA
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*
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* @rdev: radeon_device pointer
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* @ib: indirect buffer to fill with commands
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* @pe: addr of the page entry
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* @addr: dst addr to write into pe
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* @count: number of page entries to update
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* @incr: increase next addr by incr bytes
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* @flags: access flags
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*
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* Update the page tables using the DMA (SI).
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*/
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void si_dma_vm_set_pages(struct radeon_device *rdev,
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struct radeon_ib *ib,
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uint64_t pe,
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uint64_t addr, unsigned count,
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uint32_t incr, uint32_t flags)
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{
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uint64_t value;
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unsigned ndw;
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while (count) {
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ndw = count * 2;
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if (ndw > 0xFFFFE)
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ndw = 0xFFFFE;
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if (flags & R600_PTE_VALID)
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value = addr;
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else
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value = 0;
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/* for physically contiguous pages (vram) */
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ib->ptr[ib->length_dw++] = DMA_PTE_PDE_PACKET(ndw);
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ib->ptr[ib->length_dw++] = pe; /* dst addr */
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ib->ptr[ib->length_dw++] = upper_32_bits(pe) & 0xff;
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ib->ptr[ib->length_dw++] = flags; /* mask */
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ib->ptr[ib->length_dw++] = 0;
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ib->ptr[ib->length_dw++] = value; /* value */
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ib->ptr[ib->length_dw++] = upper_32_bits(value);
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ib->ptr[ib->length_dw++] = incr; /* increment size */
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ib->ptr[ib->length_dw++] = 0;
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pe += ndw * 4;
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addr += (ndw / 2) * incr;
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count -= ndw / 2;
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}
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}
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void si_dma_vm_flush(struct radeon_device *rdev, int ridx, struct radeon_vm *vm)
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{
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struct radeon_ring *ring = &rdev->ring[ridx];
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if (vm == NULL)
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return;
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radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_SRBM_WRITE, 0, 0, 0, 0));
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if (vm->id < 8) {
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radeon_ring_write(ring, (0xf << 16) | ((VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + (vm->id << 2)) >> 2));
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} else {
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radeon_ring_write(ring, (0xf << 16) | ((VM_CONTEXT8_PAGE_TABLE_BASE_ADDR + ((vm->id - 8) << 2)) >> 2));
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}
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radeon_ring_write(ring, vm->pd_gpu_addr >> 12);
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/* flush hdp cache */
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radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_SRBM_WRITE, 0, 0, 0, 0));
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radeon_ring_write(ring, (0xf << 16) | (HDP_MEM_COHERENCY_FLUSH_CNTL >> 2));
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radeon_ring_write(ring, 1);
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/* bits 0-7 are the VM contexts0-7 */
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radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_SRBM_WRITE, 0, 0, 0, 0));
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radeon_ring_write(ring, (0xf << 16) | (VM_INVALIDATE_REQUEST >> 2));
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radeon_ring_write(ring, 1 << vm->id);
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}
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/**
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* si_copy_dma - copy pages using the DMA engine
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*
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* @rdev: radeon_device pointer
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* @src_offset: src GPU address
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* @dst_offset: dst GPU address
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* @num_gpu_pages: number of GPU pages to xfer
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* @resv: reservation object to sync to
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*
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* Copy GPU paging using the DMA engine (SI).
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* Used by the radeon ttm implementation to move pages if
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* registered as the asic copy callback.
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*/
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struct radeon_fence *si_copy_dma(struct radeon_device *rdev,
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uint64_t src_offset, uint64_t dst_offset,
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unsigned num_gpu_pages,
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struct reservation_object *resv)
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{
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struct radeon_semaphore *sem = NULL;
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struct radeon_fence *fence;
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int ring_index = rdev->asic->copy.dma_ring_index;
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struct radeon_ring *ring = &rdev->ring[ring_index];
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u32 size_in_bytes, cur_size_in_bytes;
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int i, num_loops;
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int r = 0;
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r = radeon_semaphore_create(rdev, &sem);
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if (r) {
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DRM_ERROR("radeon: moving bo (%d).\n", r);
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return ERR_PTR(r);
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}
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size_in_bytes = (num_gpu_pages << RADEON_GPU_PAGE_SHIFT);
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num_loops = DIV_ROUND_UP(size_in_bytes, 0xfffff);
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r = radeon_ring_lock(rdev, ring, num_loops * 5 + 11);
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if (r) {
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DRM_ERROR("radeon: moving bo (%d).\n", r);
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radeon_semaphore_free(rdev, &sem, NULL);
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return ERR_PTR(r);
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}
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radeon_semaphore_sync_resv(rdev, sem, resv, false);
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radeon_semaphore_sync_rings(rdev, sem, ring->idx);
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for (i = 0; i < num_loops; i++) {
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cur_size_in_bytes = size_in_bytes;
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if (cur_size_in_bytes > 0xFFFFF)
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cur_size_in_bytes = 0xFFFFF;
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size_in_bytes -= cur_size_in_bytes;
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radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_COPY, 1, 0, 0, cur_size_in_bytes));
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radeon_ring_write(ring, lower_32_bits(dst_offset));
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radeon_ring_write(ring, lower_32_bits(src_offset));
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radeon_ring_write(ring, upper_32_bits(dst_offset) & 0xff);
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radeon_ring_write(ring, upper_32_bits(src_offset) & 0xff);
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src_offset += cur_size_in_bytes;
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dst_offset += cur_size_in_bytes;
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}
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r = radeon_fence_emit(rdev, &fence, ring->idx);
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if (r) {
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radeon_ring_unlock_undo(rdev, ring);
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radeon_semaphore_free(rdev, &sem, NULL);
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return ERR_PTR(r);
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}
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radeon_ring_unlock_commit(rdev, ring, false);
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radeon_semaphore_free(rdev, &sem, fence);
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return fence;
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}
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