403 lines
9.6 KiB
C
403 lines
9.6 KiB
C
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/* Copyright (c) 2013-2015, The Linux Foundation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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* only version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*/
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#define pr_fmt(fmt) "%s: " fmt, __func__
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#include <linux/kernel.h>
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#include <linux/err.h>
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#include <linux/string.h>
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#include <linux/clk/msm-clock-generic.h>
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#include <linux/of_address.h>
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#include <linux/dma-mapping.h>
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#include "mdss-pll.h"
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int mdss_pll_util_resource_init(struct platform_device *pdev,
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struct mdss_pll_resources *pll_res)
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{
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int rc = 0;
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struct dss_module_power *mp = &pll_res->mp;
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rc = msm_dss_config_vreg(&pdev->dev,
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mp->vreg_config, mp->num_vreg, 1);
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if (rc) {
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pr_err("Vreg config failed rc=%d\n", rc);
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goto vreg_err;
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}
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rc = msm_dss_get_clk(&pdev->dev, mp->clk_config, mp->num_clk);
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if (rc) {
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pr_err("Clock get failed rc=%d\n", rc);
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goto clk_err;
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}
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return rc;
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clk_err:
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msm_dss_config_vreg(&pdev->dev, mp->vreg_config, mp->num_vreg, 0);
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vreg_err:
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return rc;
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}
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/**
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* mdss_pll_get_mp_by_reg_name() -- Find power module by regulator name
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*@pll_res: Pointer to the PLL resource
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*@name: Regulator name as specified in the pll dtsi
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*
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* This is a helper function to retrieve the regulator information
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* for each pll resource.
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*/
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struct dss_vreg *mdss_pll_get_mp_by_reg_name(struct mdss_pll_resources *pll_res
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, char *name)
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{
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struct dss_vreg *regulator = NULL;
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int i;
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if ((pll_res == NULL) || (pll_res->mp.vreg_config == NULL)) {
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pr_err("%s Invalid PLL resource\n", __func__);
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goto error;
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}
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regulator = pll_res->mp.vreg_config;
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for (i = 0; i < pll_res->mp.num_vreg; i++) {
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if (!strcmp(name, regulator->vreg_name)) {
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pr_debug("Found regulator match for %s\n", name);
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break;
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}
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regulator++;
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}
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error:
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return regulator;
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}
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void mdss_pll_util_resource_deinit(struct platform_device *pdev,
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struct mdss_pll_resources *pll_res)
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{
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struct dss_module_power *mp = &pll_res->mp;
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msm_dss_put_clk(mp->clk_config, mp->num_clk);
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msm_dss_config_vreg(&pdev->dev, mp->vreg_config, mp->num_vreg, 0);
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}
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void mdss_pll_util_resource_release(struct platform_device *pdev,
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struct mdss_pll_resources *pll_res)
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{
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struct dss_module_power *mp = &pll_res->mp;
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devm_kfree(&pdev->dev, mp->clk_config);
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devm_kfree(&pdev->dev, mp->vreg_config);
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mp->num_vreg = 0;
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mp->num_clk = 0;
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}
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int mdss_pll_util_resource_enable(struct mdss_pll_resources *pll_res,
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bool enable)
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{
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int rc = 0;
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struct dss_module_power *mp = &pll_res->mp;
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if (enable) {
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rc = msm_dss_enable_vreg(mp->vreg_config, mp->num_vreg, enable);
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if (rc) {
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pr_err("Failed to enable vregs rc=%d\n", rc);
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goto vreg_err;
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}
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rc = msm_dss_clk_set_rate(mp->clk_config, mp->num_clk);
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if (rc) {
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pr_err("Failed to set clock rate rc=%d\n", rc);
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goto clk_err;
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}
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rc = msm_dss_enable_clk(mp->clk_config, mp->num_clk, enable);
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if (rc) {
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pr_err("clock enable failed rc:%d\n", rc);
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goto clk_err;
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}
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} else {
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msm_dss_enable_clk(mp->clk_config, mp->num_clk, enable);
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msm_dss_enable_vreg(mp->vreg_config, mp->num_vreg, enable);
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}
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return rc;
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clk_err:
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msm_dss_enable_vreg(mp->vreg_config, mp->num_vreg, 0);
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vreg_err:
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return rc;
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}
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static int mdss_pll_util_parse_dt_supply(struct platform_device *pdev,
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struct mdss_pll_resources *pll_res)
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{
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int i = 0, rc = 0;
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u32 tmp = 0;
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struct device_node *of_node = NULL, *supply_root_node = NULL;
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struct device_node *supply_node = NULL;
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struct dss_module_power *mp = &pll_res->mp;
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of_node = pdev->dev.of_node;
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mp->num_vreg = 0;
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supply_root_node = of_get_child_by_name(of_node,
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"qcom,platform-supply-entries");
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if (!supply_root_node) {
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pr_err("no supply entry present\n");
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return rc;
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}
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for_each_child_of_node(supply_root_node, supply_node) {
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mp->num_vreg++;
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}
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if (mp->num_vreg == 0) {
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pr_debug("no vreg\n");
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return rc;
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} else {
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pr_debug("vreg found. count=%d\n", mp->num_vreg);
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}
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mp->vreg_config = devm_kzalloc(&pdev->dev, sizeof(struct dss_vreg) *
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mp->num_vreg, GFP_KERNEL);
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if (!mp->vreg_config) {
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pr_err("can't alloc vreg mem\n");
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rc = -ENOMEM;
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return rc;
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}
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for_each_child_of_node(supply_root_node, supply_node) {
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const char *st = NULL;
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rc = of_property_read_string(supply_node,
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"qcom,supply-name", &st);
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if (rc) {
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pr_err(":error reading name. rc=%d\n", rc);
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goto error;
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}
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strlcpy(mp->vreg_config[i].vreg_name, st,
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sizeof(mp->vreg_config[i].vreg_name));
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rc = of_property_read_u32(supply_node,
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"qcom,supply-min-voltage", &tmp);
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if (rc) {
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pr_err(": error reading min volt. rc=%d\n", rc);
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goto error;
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}
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mp->vreg_config[i].min_voltage = tmp;
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rc = of_property_read_u32(supply_node,
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"qcom,supply-max-voltage", &tmp);
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if (rc) {
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pr_err(": error reading max volt. rc=%d\n", rc);
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goto error;
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}
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mp->vreg_config[i].max_voltage = tmp;
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rc = of_property_read_u32(supply_node,
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"qcom,supply-enable-load", &tmp);
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if (rc) {
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pr_err(": error reading enable load. rc=%d\n", rc);
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goto error;
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}
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mp->vreg_config[i].enable_load = tmp;
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rc = of_property_read_u32(supply_node,
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"qcom,supply-disable-load", &tmp);
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if (rc) {
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pr_err(": error reading disable load. rc=%d\n", rc);
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goto error;
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}
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mp->vreg_config[i].disable_load = tmp;
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rc = of_property_read_u32(supply_node,
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"qcom,supply-pre-on-sleep", &tmp);
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if (rc)
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pr_debug("error reading supply pre sleep value. rc=%d\n",
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rc);
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mp->vreg_config[i].pre_on_sleep = (!rc ? tmp : 0);
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rc = of_property_read_u32(supply_node,
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"qcom,supply-pre-off-sleep", &tmp);
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if (rc)
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pr_debug("error reading supply pre sleep value. rc=%d\n",
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rc);
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mp->vreg_config[i].pre_off_sleep = (!rc ? tmp : 0);
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rc = of_property_read_u32(supply_node,
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"qcom,supply-post-on-sleep", &tmp);
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if (rc)
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pr_debug("error reading supply post sleep value. rc=%d\n",
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rc);
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mp->vreg_config[i].post_on_sleep = (!rc ? tmp : 0);
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rc = of_property_read_u32(supply_node,
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"qcom,supply-post-off-sleep", &tmp);
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if (rc)
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pr_debug("error reading supply post sleep value. rc=%d\n",
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rc);
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mp->vreg_config[i].post_off_sleep = (!rc ? tmp : 0);
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pr_debug("%s min=%d, max=%d, enable=%d, disable=%d, preonsleep=%d, postonsleep=%d, preoffsleep=%d, postoffsleep=%d\n",
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mp->vreg_config[i].vreg_name,
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mp->vreg_config[i].min_voltage,
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mp->vreg_config[i].max_voltage,
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mp->vreg_config[i].enable_load,
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mp->vreg_config[i].disable_load,
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mp->vreg_config[i].pre_on_sleep,
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mp->vreg_config[i].post_on_sleep,
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mp->vreg_config[i].pre_off_sleep,
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mp->vreg_config[i].post_off_sleep);
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++i;
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rc = 0;
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}
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return rc;
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error:
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if (mp->vreg_config) {
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devm_kfree(&pdev->dev, mp->vreg_config);
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mp->vreg_config = NULL;
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mp->num_vreg = 0;
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}
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return rc;
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}
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static int mdss_pll_util_parse_dt_clock(struct platform_device *pdev,
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struct mdss_pll_resources *pll_res)
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{
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u32 i = 0, rc = 0;
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struct dss_module_power *mp = &pll_res->mp;
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const char *clock_name;
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u32 clock_rate;
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mp->num_clk = of_property_count_strings(pdev->dev.of_node,
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"clock-names");
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if (mp->num_clk <= 0) {
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pr_err("clocks are not defined\n");
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goto clk_err;
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}
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mp->clk_config = devm_kzalloc(&pdev->dev,
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sizeof(struct dss_clk) * mp->num_clk, GFP_KERNEL);
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if (!mp->clk_config) {
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pr_err("clock configuration allocation failed\n");
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rc = -ENOMEM;
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mp->num_clk = 0;
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goto clk_err;
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}
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for (i = 0; i < mp->num_clk; i++) {
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of_property_read_string_index(pdev->dev.of_node, "clock-names",
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i, &clock_name);
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strlcpy(mp->clk_config[i].clk_name, clock_name,
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sizeof(mp->clk_config[i].clk_name));
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of_property_read_u32_index(pdev->dev.of_node, "clock-rate",
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i, &clock_rate);
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mp->clk_config[i].rate = clock_rate;
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if (!clock_rate)
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mp->clk_config[i].type = DSS_CLK_AHB;
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else
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mp->clk_config[i].type = DSS_CLK_PCLK;
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}
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clk_err:
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return rc;
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}
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static int mdss_pll_util_parse_dt_dfps(struct platform_device *pdev,
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struct mdss_pll_resources *pll_res)
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{
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int rc = 0;
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struct device_node *pnode;
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void __iomem *addr;
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pnode = of_parse_phandle(pdev->dev.of_node, "memory-region", 0);
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if (IS_ERR_OR_NULL(pnode)) {
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rc = PTR_ERR(pnode);
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goto pnode_err;
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}
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/* get the physical address for pll codes */
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addr = of_iomap(pnode, 0);
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if (IS_ERR_OR_NULL(addr)) {
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rc = PTR_ERR(addr);
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pr_err("couldn't get dfps physical address\n");
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goto pnode_err;
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}
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pll_res->dfps = kzalloc(sizeof(struct dfps_info), GFP_KERNEL);
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if (IS_ERR_OR_NULL(pll_res->dfps)) {
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rc = PTR_ERR(pll_res->dfps);
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pr_err("couldn't allocate dfps kernel memory\n");
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goto addr_err;
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}
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/* memcopy complete dfps structure from physical memory */
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memcpy_fromio(pll_res->dfps, addr, sizeof(struct dfps_info));
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addr_err:
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iounmap(addr);
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pnode_err:
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if (pnode)
|
||
|
|
of_node_put(pnode);
|
||
|
|
|
||
|
|
dma_release_declared_memory(&pdev->dev);
|
||
|
|
return rc;
|
||
|
|
}
|
||
|
|
|
||
|
|
int mdss_pll_util_resource_parse(struct platform_device *pdev,
|
||
|
|
struct mdss_pll_resources *pll_res)
|
||
|
|
{
|
||
|
|
int rc = 0;
|
||
|
|
struct dss_module_power *mp = &pll_res->mp;
|
||
|
|
|
||
|
|
rc = mdss_pll_util_parse_dt_supply(pdev, pll_res);
|
||
|
|
if (rc) {
|
||
|
|
pr_err("vreg parsing failed rc=%d\n", rc);
|
||
|
|
goto end;
|
||
|
|
}
|
||
|
|
|
||
|
|
rc = mdss_pll_util_parse_dt_clock(pdev, pll_res);
|
||
|
|
if (rc) {
|
||
|
|
pr_err("clock name parsing failed rc=%d", rc);
|
||
|
|
goto clk_err;
|
||
|
|
}
|
||
|
|
|
||
|
|
if (mdss_pll_util_parse_dt_dfps(pdev, pll_res))
|
||
|
|
pr_err("dfps not enabled!\n");
|
||
|
|
|
||
|
|
return rc;
|
||
|
|
|
||
|
|
clk_err:
|
||
|
|
devm_kfree(&pdev->dev, mp->vreg_config);
|
||
|
|
mp->num_vreg = 0;
|
||
|
|
end:
|
||
|
|
return rc;
|
||
|
|
}
|