522 lines
13 KiB
C
522 lines
13 KiB
C
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/* Copyright (c) 2012-2015, The Linux Foundation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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* only version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*/
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#define pr_fmt(fmt) "%s: " fmt, __func__
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#include <linux/kernel.h>
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#include <linux/err.h>
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#include <linux/delay.h>
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#include <linux/clk/msm-clk.h>
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#include <linux/clk/msm-clock-generic.h>
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#include <linux/clk/msm-clk-provider.h>
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#include <dt-bindings/clock/msm-clocks-8952.h>
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#include "mdss-pll.h"
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#include "mdss-dsi-pll.h"
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#define VCO_DELAY_USEC 1000
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static struct clk_div_ops fixed_2div_ops;
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static struct clk_ops byte_mux_clk_ops;
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static struct clk_ops pixel_clk_src_ops;
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static struct clk_ops byte_clk_src_ops;
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static struct clk_ops analog_postdiv_clk_ops;
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static struct lpfr_cfg lpfr_lut_struct[] = {
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{479500000, 8},
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{480000000, 11},
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{575500000, 8},
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{576000000, 12},
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{610500000, 8},
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{659500000, 9},
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{671500000, 10},
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{672000000, 14},
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{708500000, 10},
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{750000000, 11},
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};
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static int vco_set_rate_lpm(struct clk *c, unsigned long rate)
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{
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int rc;
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struct dsi_pll_vco_clk *vco = to_vco_clk(c);
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struct mdss_pll_resources *dsi_pll_res = vco->priv;
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rc = mdss_pll_resource_enable(dsi_pll_res, true);
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if (rc) {
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pr_err("Failed to enable mdss dsi pll resources\n");
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return rc;
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}
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/*
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* DSI PLL software reset. Add HW recommended delays after toggling
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* the software reset bit off and back on.
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*/
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MDSS_PLL_REG_W(dsi_pll_res->pll_base,
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DSI_PHY_PLL_UNIPHY_PLL_TEST_CFG, 0x01);
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udelay(1000);
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MDSS_PLL_REG_W(dsi_pll_res->pll_base,
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DSI_PHY_PLL_UNIPHY_PLL_TEST_CFG, 0x00);
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udelay(1000);
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rc = vco_set_rate(vco, rate);
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mdss_pll_resource_enable(dsi_pll_res, false);
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return rc;
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}
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static void dsi_pll_sw_reset_8916(struct mdss_pll_resources *dsi_pll_res)
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{
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/*
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* DSI PLL software reset. Add HW recommended delays after toggling
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* the software reset bit off and back on.
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*/
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MDSS_PLL_REG_W(dsi_pll_res->pll_base,
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DSI_PHY_PLL_UNIPHY_PLL_TEST_CFG, 0x01);
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ndelay(500);
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MDSS_PLL_REG_W(dsi_pll_res->pll_base,
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DSI_PHY_PLL_UNIPHY_PLL_TEST_CFG, 0x00);
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}
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static void dsi_pll_toggle_lock_detect_8916(
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struct mdss_pll_resources *dsi_pll_res)
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{
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/* DSI PLL toggle lock detect setting */
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MDSS_PLL_REG_W(dsi_pll_res->pll_base,
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DSI_PHY_PLL_UNIPHY_PLL_LKDET_CFG2, 0x04);
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ndelay(500);
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MDSS_PLL_REG_W(dsi_pll_res->pll_base,
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DSI_PHY_PLL_UNIPHY_PLL_LKDET_CFG2, 0x05);
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udelay(512);
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}
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static int dsi_pll_check_lock_status_8916(
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struct mdss_pll_resources *dsi_pll_res)
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{
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int rc = 0;
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rc = dsi_pll_lock_status(dsi_pll_res);
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if (rc)
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pr_debug("PLL Locked\n");
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else
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pr_err("PLL failed to lock\n");
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return rc;
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}
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static int gf_2_dsi_pll_enable_seq_8916(struct mdss_pll_resources *dsi_pll_res)
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{
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int pll_locked = 0;
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dsi_pll_sw_reset_8916(dsi_pll_res);
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/*
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* GF PART 2 PLL power up sequence.
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* Add necessary delays recommended by hardware.
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*/
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MDSS_PLL_REG_W(dsi_pll_res->pll_base,
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DSI_PHY_PLL_UNIPHY_PLL_CAL_CFG1, 0x04);
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MDSS_PLL_REG_W(dsi_pll_res->pll_base,
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DSI_PHY_PLL_UNIPHY_PLL_GLB_CFG, 0x01);
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MDSS_PLL_REG_W(dsi_pll_res->pll_base,
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DSI_PHY_PLL_UNIPHY_PLL_GLB_CFG, 0x05);
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udelay(3);
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MDSS_PLL_REG_W(dsi_pll_res->pll_base,
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DSI_PHY_PLL_UNIPHY_PLL_GLB_CFG, 0x0f);
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udelay(500);
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dsi_pll_toggle_lock_detect_8916(dsi_pll_res);
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pll_locked = dsi_pll_check_lock_status_8916(dsi_pll_res);
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return pll_locked ? 0 : -EINVAL;
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}
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static int gf_1_dsi_pll_enable_seq_8916(struct mdss_pll_resources *dsi_pll_res)
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{
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int pll_locked = 0;
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dsi_pll_sw_reset_8916(dsi_pll_res);
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/*
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* GF PART 1 PLL power up sequence.
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* Add necessary delays recommended by hardware.
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*/
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MDSS_PLL_REG_W(dsi_pll_res->pll_base,
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DSI_PHY_PLL_UNIPHY_PLL_CAL_CFG1, 0x14);
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MDSS_PLL_REG_W(dsi_pll_res->pll_base,
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DSI_PHY_PLL_UNIPHY_PLL_GLB_CFG, 0x01);
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MDSS_PLL_REG_W(dsi_pll_res->pll_base,
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DSI_PHY_PLL_UNIPHY_PLL_GLB_CFG, 0x05);
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udelay(3);
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MDSS_PLL_REG_W(dsi_pll_res->pll_base,
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DSI_PHY_PLL_UNIPHY_PLL_GLB_CFG, 0x0f);
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udelay(500);
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dsi_pll_toggle_lock_detect_8916(dsi_pll_res);
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pll_locked = dsi_pll_check_lock_status_8916(dsi_pll_res);
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return pll_locked ? 0 : -EINVAL;
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}
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static int tsmc_dsi_pll_enable_seq_8916(struct mdss_pll_resources *dsi_pll_res)
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{
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int pll_locked = 0;
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dsi_pll_sw_reset_8916(dsi_pll_res);
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/*
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* TSMC PLL power up sequence.
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* Add necessary delays recommended by hardware.
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*/
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MDSS_PLL_REG_W(dsi_pll_res->pll_base,
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DSI_PHY_PLL_UNIPHY_PLL_CAL_CFG1, 0x34);
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MDSS_PLL_REG_W(dsi_pll_res->pll_base,
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DSI_PHY_PLL_UNIPHY_PLL_GLB_CFG, 0x01);
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MDSS_PLL_REG_W(dsi_pll_res->pll_base,
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DSI_PHY_PLL_UNIPHY_PLL_GLB_CFG, 0x05);
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MDSS_PLL_REG_W(dsi_pll_res->pll_base,
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DSI_PHY_PLL_UNIPHY_PLL_GLB_CFG, 0x0f);
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udelay(500);
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dsi_pll_toggle_lock_detect_8916(dsi_pll_res);
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pll_locked = dsi_pll_check_lock_status_8916(dsi_pll_res);
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return pll_locked ? 0 : -EINVAL;
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}
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/* Op structures */
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static struct clk_ops clk_ops_dsi_vco = {
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.set_rate = vco_set_rate_lpm,
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.round_rate = vco_round_rate,
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.handoff = vco_handoff,
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.prepare = vco_prepare,
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.unprepare = vco_unprepare,
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};
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static struct clk_div_ops fixed_4div_ops = {
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.set_div = fixed_4div_set_div,
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.get_div = fixed_4div_get_div,
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};
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static struct clk_div_ops analog_postdiv_ops = {
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.set_div = analog_set_div,
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.get_div = analog_get_div,
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};
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static struct clk_div_ops digital_postdiv_ops = {
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.set_div = digital_set_div,
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.get_div = digital_get_div,
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};
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static struct clk_mux_ops byte_mux_ops = {
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.set_mux_sel = set_byte_mux_sel,
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.get_mux_sel = get_byte_mux_sel,
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};
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/* DSI PLL0 clock structures */
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static struct dsi_pll_vco_clk dsi_pll0_vco_clk = {
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.ref_clk_rate = 19200000,
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.min_rate = 350000000,
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.max_rate = 750000000,
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.pll_en_seq_cnt = 9,
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.pll_enable_seqs[0] = tsmc_dsi_pll_enable_seq_8916,
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.pll_enable_seqs[1] = tsmc_dsi_pll_enable_seq_8916,
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.pll_enable_seqs[2] = tsmc_dsi_pll_enable_seq_8916,
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.pll_enable_seqs[3] = gf_1_dsi_pll_enable_seq_8916,
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.pll_enable_seqs[4] = gf_1_dsi_pll_enable_seq_8916,
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.pll_enable_seqs[5] = gf_1_dsi_pll_enable_seq_8916,
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.pll_enable_seqs[6] = gf_2_dsi_pll_enable_seq_8916,
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.pll_enable_seqs[7] = gf_2_dsi_pll_enable_seq_8916,
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.pll_enable_seqs[8] = gf_2_dsi_pll_enable_seq_8916,
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.lpfr_lut_size = 10,
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.lpfr_lut = lpfr_lut_struct,
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.c = {
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.dbg_name = "dsi_pll0_vco_clk",
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.ops = &clk_ops_dsi_vco,
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CLK_INIT(dsi_pll0_vco_clk.c),
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},
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};
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static struct div_clk dsi_pll0_analog_postdiv_clk = {
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.data = {
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.max_div = 255,
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.min_div = 1,
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},
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.ops = &analog_postdiv_ops,
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.c = {
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.parent = &dsi_pll0_vco_clk.c,
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.dbg_name = "dsi_pll0_analog_postdiv_clk",
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.ops = &analog_postdiv_clk_ops,
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.flags = CLKFLAG_NO_RATE_CACHE,
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CLK_INIT(dsi_pll0_analog_postdiv_clk.c),
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},
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};
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static struct div_clk dsi_pll0_indirect_path_div2_clk = {
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.ops = &fixed_2div_ops,
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.data = {
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.div = 2,
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.min_div = 2,
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.max_div = 2,
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},
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.c = {
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.parent = &dsi_pll0_analog_postdiv_clk.c,
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.dbg_name = "dsi_pll0_indirect_path_div2_clk",
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.ops = &clk_ops_div,
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.flags = CLKFLAG_NO_RATE_CACHE,
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CLK_INIT(dsi_pll0_indirect_path_div2_clk.c),
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},
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};
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static struct div_clk dsi_pll0_pixel_clk_src = {
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.data = {
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.max_div = 255,
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.min_div = 1,
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},
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.ops = &digital_postdiv_ops,
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.c = {
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.parent = &dsi_pll0_vco_clk.c,
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.dbg_name = "dsi_pll0_pixel_clk_src",
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.ops = &pixel_clk_src_ops,
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.flags = CLKFLAG_NO_RATE_CACHE,
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CLK_INIT(dsi_pll0_pixel_clk_src.c),
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},
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};
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static struct mux_clk dsi_pll0_byte_mux = {
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.num_parents = 2,
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.parents = (struct clk_src[]){
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{&dsi_pll0_vco_clk.c, 0},
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{&dsi_pll0_indirect_path_div2_clk.c, 1},
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},
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.ops = &byte_mux_ops,
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.c = {
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.parent = &dsi_pll0_vco_clk.c,
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.dbg_name = "dsi_pll0_byte_mux",
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.ops = &byte_mux_clk_ops,
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CLK_INIT(dsi_pll0_byte_mux.c),
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},
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};
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static struct div_clk dsi_pll0_byte_clk_src = {
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.ops = &fixed_4div_ops,
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.data = {
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.min_div = 4,
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.max_div = 4,
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},
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.c = {
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.parent = &dsi_pll0_byte_mux.c,
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.dbg_name = "dsi_pll0_byte_clk_src",
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.ops = &byte_clk_src_ops,
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CLK_INIT(dsi_pll0_byte_clk_src.c),
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},
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};
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/* DSI PLL1 clock structures */
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static struct dsi_pll_vco_clk dsi_pll1_vco_clk = {
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.ref_clk_rate = 19200000,
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.min_rate = 350000000,
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.max_rate = 750000000,
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.pll_en_seq_cnt = 9,
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.pll_enable_seqs[0] = tsmc_dsi_pll_enable_seq_8916,
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.pll_enable_seqs[1] = tsmc_dsi_pll_enable_seq_8916,
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.pll_enable_seqs[2] = tsmc_dsi_pll_enable_seq_8916,
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.pll_enable_seqs[3] = gf_1_dsi_pll_enable_seq_8916,
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.pll_enable_seqs[4] = gf_1_dsi_pll_enable_seq_8916,
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.pll_enable_seqs[5] = gf_1_dsi_pll_enable_seq_8916,
|
||
|
|
.pll_enable_seqs[6] = gf_2_dsi_pll_enable_seq_8916,
|
||
|
|
.pll_enable_seqs[7] = gf_2_dsi_pll_enable_seq_8916,
|
||
|
|
.pll_enable_seqs[8] = gf_2_dsi_pll_enable_seq_8916,
|
||
|
|
.lpfr_lut_size = 10,
|
||
|
|
.lpfr_lut = lpfr_lut_struct,
|
||
|
|
.c = {
|
||
|
|
.dbg_name = "dsi_pll1_vco_clk",
|
||
|
|
.ops = &clk_ops_dsi_vco,
|
||
|
|
CLK_INIT(dsi_pll1_vco_clk.c),
|
||
|
|
},
|
||
|
|
};
|
||
|
|
|
||
|
|
static struct div_clk dsi_pll1_analog_postdiv_clk = {
|
||
|
|
.data = {
|
||
|
|
.max_div = 255,
|
||
|
|
.min_div = 1,
|
||
|
|
},
|
||
|
|
.ops = &analog_postdiv_ops,
|
||
|
|
.c = {
|
||
|
|
.parent = &dsi_pll1_vco_clk.c,
|
||
|
|
.dbg_name = "dsi_pll1_analog_postdiv_clk",
|
||
|
|
.ops = &analog_postdiv_clk_ops,
|
||
|
|
.flags = CLKFLAG_NO_RATE_CACHE,
|
||
|
|
CLK_INIT(dsi_pll1_analog_postdiv_clk.c),
|
||
|
|
},
|
||
|
|
};
|
||
|
|
|
||
|
|
static struct div_clk dsi_pll1_indirect_path_div2_clk = {
|
||
|
|
.ops = &fixed_2div_ops,
|
||
|
|
.data = {
|
||
|
|
.div = 2,
|
||
|
|
.min_div = 2,
|
||
|
|
.max_div = 2,
|
||
|
|
},
|
||
|
|
.c = {
|
||
|
|
.parent = &dsi_pll1_analog_postdiv_clk.c,
|
||
|
|
.dbg_name = "dsi_pll1_indirect_path_div2_clk",
|
||
|
|
.ops = &clk_ops_div,
|
||
|
|
.flags = CLKFLAG_NO_RATE_CACHE,
|
||
|
|
CLK_INIT(dsi_pll1_indirect_path_div2_clk.c),
|
||
|
|
},
|
||
|
|
};
|
||
|
|
|
||
|
|
static struct div_clk dsi_pll1_pixel_clk_src = {
|
||
|
|
.data = {
|
||
|
|
.max_div = 255,
|
||
|
|
.min_div = 1,
|
||
|
|
},
|
||
|
|
.ops = &digital_postdiv_ops,
|
||
|
|
.c = {
|
||
|
|
.parent = &dsi_pll1_vco_clk.c,
|
||
|
|
.dbg_name = "dsi_pll1_pixel_clk_src",
|
||
|
|
.ops = &pixel_clk_src_ops,
|
||
|
|
.flags = CLKFLAG_NO_RATE_CACHE,
|
||
|
|
CLK_INIT(dsi_pll1_pixel_clk_src.c),
|
||
|
|
},
|
||
|
|
};
|
||
|
|
|
||
|
|
static struct mux_clk dsi_pll1_byte_mux = {
|
||
|
|
.num_parents = 2,
|
||
|
|
.parents = (struct clk_src[]){
|
||
|
|
{&dsi_pll1_vco_clk.c, 0},
|
||
|
|
{&dsi_pll1_indirect_path_div2_clk.c, 1},
|
||
|
|
},
|
||
|
|
.ops = &byte_mux_ops,
|
||
|
|
.c = {
|
||
|
|
.parent = &dsi_pll1_vco_clk.c,
|
||
|
|
.dbg_name = "dsi_pll1_byte_mux",
|
||
|
|
.ops = &byte_mux_clk_ops,
|
||
|
|
CLK_INIT(dsi_pll1_byte_mux.c),
|
||
|
|
},
|
||
|
|
};
|
||
|
|
|
||
|
|
static struct div_clk dsi_pll1_byte_clk_src = {
|
||
|
|
.ops = &fixed_4div_ops,
|
||
|
|
.data = {
|
||
|
|
.min_div = 4,
|
||
|
|
.max_div = 4,
|
||
|
|
},
|
||
|
|
.c = {
|
||
|
|
.parent = &dsi_pll1_byte_mux.c,
|
||
|
|
.dbg_name = "dsi_pll1_byte_clk_src",
|
||
|
|
.ops = &byte_clk_src_ops,
|
||
|
|
CLK_INIT(dsi_pll1_byte_clk_src.c),
|
||
|
|
},
|
||
|
|
};
|
||
|
|
|
||
|
|
static struct clk_lookup dsi_pll0_cc[] = {
|
||
|
|
CLK_LIST(dsi_pll0_pixel_clk_src),
|
||
|
|
CLK_LIST(dsi_pll0_byte_clk_src),
|
||
|
|
};
|
||
|
|
|
||
|
|
static struct clk_lookup dsi_pll1_cc[] = {
|
||
|
|
CLK_LIST(dsi_pll1_pixel_clk_src),
|
||
|
|
CLK_LIST(dsi_pll1_byte_clk_src),
|
||
|
|
};
|
||
|
|
|
||
|
|
int dsi_pll_clock_register_lpm(struct platform_device *pdev,
|
||
|
|
struct mdss_pll_resources *pll_res)
|
||
|
|
{
|
||
|
|
int rc;
|
||
|
|
int const ssc_freq_min = 30000; /* min. recommended freq. value */
|
||
|
|
int const ssc_freq_max = 33000; /* max. recommended freq. value */
|
||
|
|
int const ssc_ppm_max = 5000; /* max. recommended ppm */
|
||
|
|
|
||
|
|
if (!pdev || !pdev->dev.of_node) {
|
||
|
|
pr_err("Invalid input parameters\n");
|
||
|
|
return -EINVAL;
|
||
|
|
}
|
||
|
|
|
||
|
|
if (!pll_res || !pll_res->pll_base) {
|
||
|
|
pr_err("Invalid PLL resources\n");
|
||
|
|
return -EPROBE_DEFER;
|
||
|
|
}
|
||
|
|
|
||
|
|
/* Set client data to mux, div and vco clocks */
|
||
|
|
if (!pll_res->index) {
|
||
|
|
dsi_pll0_byte_clk_src.priv = pll_res;
|
||
|
|
dsi_pll0_pixel_clk_src.priv = pll_res;
|
||
|
|
dsi_pll0_byte_mux.priv = pll_res;
|
||
|
|
dsi_pll0_indirect_path_div2_clk.priv = pll_res;
|
||
|
|
dsi_pll0_analog_postdiv_clk.priv = pll_res;
|
||
|
|
dsi_pll0_vco_clk.priv = pll_res;
|
||
|
|
} else {
|
||
|
|
dsi_pll1_byte_clk_src.priv = pll_res;
|
||
|
|
dsi_pll1_pixel_clk_src.priv = pll_res;
|
||
|
|
dsi_pll1_byte_mux.priv = pll_res;
|
||
|
|
dsi_pll1_indirect_path_div2_clk.priv = pll_res;
|
||
|
|
dsi_pll1_analog_postdiv_clk.priv = pll_res;
|
||
|
|
dsi_pll1_vco_clk.priv = pll_res;
|
||
|
|
}
|
||
|
|
|
||
|
|
pll_res->vco_delay = VCO_DELAY_USEC;
|
||
|
|
|
||
|
|
/* Set clock source operations */
|
||
|
|
pixel_clk_src_ops = clk_ops_slave_div;
|
||
|
|
pixel_clk_src_ops.prepare = dsi_pll_div_prepare;
|
||
|
|
|
||
|
|
analog_postdiv_clk_ops = clk_ops_div;
|
||
|
|
analog_postdiv_clk_ops.prepare = dsi_pll_div_prepare;
|
||
|
|
|
||
|
|
byte_clk_src_ops = clk_ops_div;
|
||
|
|
byte_clk_src_ops.prepare = dsi_pll_div_prepare;
|
||
|
|
|
||
|
|
byte_mux_clk_ops = clk_ops_gen_mux;
|
||
|
|
byte_mux_clk_ops.prepare = dsi_pll_mux_prepare;
|
||
|
|
|
||
|
|
if (pll_res->ssc_en) {
|
||
|
|
if (!pll_res->ssc_freq || (pll_res->ssc_freq < ssc_freq_min) ||
|
||
|
|
(pll_res->ssc_freq > ssc_freq_max)) {
|
||
|
|
pll_res->ssc_freq = ssc_freq_min;
|
||
|
|
pr_debug("SSC frequency out of recommended range. Set to default=%d\n",
|
||
|
|
pll_res->ssc_freq);
|
||
|
|
}
|
||
|
|
|
||
|
|
if (!pll_res->ssc_ppm || (pll_res->ssc_ppm > ssc_ppm_max)) {
|
||
|
|
pll_res->ssc_ppm = ssc_ppm_max;
|
||
|
|
pr_debug("SSC PPM out of recommended range. Set to default=%d\n",
|
||
|
|
pll_res->ssc_ppm);
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
if ((pll_res->target_id == MDSS_PLL_TARGET_8952) ||
|
||
|
|
(pll_res->target_id == MDSS_PLL_TARGET_8937)) {
|
||
|
|
if (!pll_res->index)
|
||
|
|
rc = of_msm_clock_register(pdev->dev.of_node,
|
||
|
|
dsi_pll0_cc, ARRAY_SIZE(dsi_pll0_cc));
|
||
|
|
else
|
||
|
|
rc = of_msm_clock_register(pdev->dev.of_node,
|
||
|
|
dsi_pll1_cc, ARRAY_SIZE(dsi_pll1_cc));
|
||
|
|
if (rc) {
|
||
|
|
pr_err("Clock register failed\n");
|
||
|
|
rc = -EPROBE_DEFER;
|
||
|
|
}
|
||
|
|
} else {
|
||
|
|
pr_err("Invalid target ID\n");
|
||
|
|
rc = -EINVAL;
|
||
|
|
}
|
||
|
|
|
||
|
|
if (!rc)
|
||
|
|
pr_info("Registered DSI PLL:%d clocks successfully\n",
|
||
|
|
pll_res->index);
|
||
|
|
|
||
|
|
return rc;
|
||
|
|
}
|