230 lines
6.3 KiB
C
230 lines
6.3 KiB
C
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/*
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* PKUnity Ultra Media Access Layer (UMAL) Ethernet MAC Registers
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*/
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/* MAC module of UMAL */
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/* UMAL's MAC module includes G/MII interface, several additional PHY
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* interfaces, and MAC control sub-layer, which provides support for control
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* frames (e.g. PAUSE frames).
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*/
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/*
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* TX/RX reset and control UMAL_CFG1
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*/
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#define UMAL_CFG1 (PKUNITY_UMAL_BASE + 0x0000)
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/*
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* MAC interface mode control UMAL_CFG2
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*/
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#define UMAL_CFG2 (PKUNITY_UMAL_BASE + 0x0004)
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/*
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* Inter Packet/Frame Gap UMAL_IPGIFG
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*/
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#define UMAL_IPGIFG (PKUNITY_UMAL_BASE + 0x0008)
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/*
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* Collision retry or backoff UMAL_HALFDUPLEX
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*/
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#define UMAL_HALFDUPLEX (PKUNITY_UMAL_BASE + 0x000c)
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/*
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* Maximum Frame Length UMAL_MAXFRAME
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*/
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#define UMAL_MAXFRAME (PKUNITY_UMAL_BASE + 0x0010)
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/*
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* Test Regsiter UMAL_TESTREG
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*/
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#define UMAL_TESTREG (PKUNITY_UMAL_BASE + 0x001c)
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/*
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* MII Management Configure UMAL_MIICFG
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*/
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#define UMAL_MIICFG (PKUNITY_UMAL_BASE + 0x0020)
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/*
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* MII Management Command UMAL_MIICMD
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*/
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#define UMAL_MIICMD (PKUNITY_UMAL_BASE + 0x0024)
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/*
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* MII Management Address UMAL_MIIADDR
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*/
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#define UMAL_MIIADDR (PKUNITY_UMAL_BASE + 0x0028)
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/*
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* MII Management Control UMAL_MIICTRL
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*/
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#define UMAL_MIICTRL (PKUNITY_UMAL_BASE + 0x002c)
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/*
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* MII Management Status UMAL_MIISTATUS
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*/
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#define UMAL_MIISTATUS (PKUNITY_UMAL_BASE + 0x0030)
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/*
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* MII Management Indicator UMAL_MIIIDCT
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*/
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#define UMAL_MIIIDCT (PKUNITY_UMAL_BASE + 0x0034)
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/*
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* Interface Control UMAL_IFCTRL
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*/
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#define UMAL_IFCTRL (PKUNITY_UMAL_BASE + 0x0038)
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/*
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* Interface Status UMAL_IFSTATUS
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*/
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#define UMAL_IFSTATUS (PKUNITY_UMAL_BASE + 0x003c)
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/*
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* MAC address (high 4 bytes) UMAL_STADDR1
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*/
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#define UMAL_STADDR1 (PKUNITY_UMAL_BASE + 0x0040)
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/*
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* MAC address (low 2 bytes) UMAL_STADDR2
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*/
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#define UMAL_STADDR2 (PKUNITY_UMAL_BASE + 0x0044)
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/* FIFO MODULE OF UMAL */
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/* UMAL's FIFO module provides data queuing for increased system level
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* throughput
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*/
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#define UMAL_FIFOCFG0 (PKUNITY_UMAL_BASE + 0x0048)
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#define UMAL_FIFOCFG1 (PKUNITY_UMAL_BASE + 0x004c)
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#define UMAL_FIFOCFG2 (PKUNITY_UMAL_BASE + 0x0050)
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#define UMAL_FIFOCFG3 (PKUNITY_UMAL_BASE + 0x0054)
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#define UMAL_FIFOCFG4 (PKUNITY_UMAL_BASE + 0x0058)
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#define UMAL_FIFOCFG5 (PKUNITY_UMAL_BASE + 0x005c)
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#define UMAL_FIFORAM0 (PKUNITY_UMAL_BASE + 0x0060)
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#define UMAL_FIFORAM1 (PKUNITY_UMAL_BASE + 0x0064)
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#define UMAL_FIFORAM2 (PKUNITY_UMAL_BASE + 0x0068)
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#define UMAL_FIFORAM3 (PKUNITY_UMAL_BASE + 0x006c)
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#define UMAL_FIFORAM4 (PKUNITY_UMAL_BASE + 0x0070)
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#define UMAL_FIFORAM5 (PKUNITY_UMAL_BASE + 0x0074)
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#define UMAL_FIFORAM6 (PKUNITY_UMAL_BASE + 0x0078)
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#define UMAL_FIFORAM7 (PKUNITY_UMAL_BASE + 0x007c)
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/* MAHBE MODULE OF UMAL */
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/* UMAL's MAHBE module interfaces to the host system through 32-bit AHB Master
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* and Slave ports.Registers within the M-AHBE provide Control and Status
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* information concerning these transfers.
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*/
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/*
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* Transmit Control UMAL_DMATxCtrl
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*/
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#define UMAL_DMATxCtrl (PKUNITY_UMAL_BASE + 0x0180)
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/*
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* Pointer to TX Descripter UMAL_DMATxDescriptor
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*/
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#define UMAL_DMATxDescriptor (PKUNITY_UMAL_BASE + 0x0184)
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/*
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* Status of Tx Packet Transfers UMAL_DMATxStatus
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*/
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#define UMAL_DMATxStatus (PKUNITY_UMAL_BASE + 0x0188)
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/*
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* Receive Control UMAL_DMARxCtrl
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*/
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#define UMAL_DMARxCtrl (PKUNITY_UMAL_BASE + 0x018c)
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/*
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* Pointer to Rx Descriptor UMAL_DMARxDescriptor
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*/
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#define UMAL_DMARxDescriptor (PKUNITY_UMAL_BASE + 0x0190)
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/*
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* Status of Rx Packet Transfers UMAL_DMARxStatus
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*/
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#define UMAL_DMARxStatus (PKUNITY_UMAL_BASE + 0x0194)
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/*
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* Interrupt Mask UMAL_DMAIntrMask
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*/
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#define UMAL_DMAIntrMask (PKUNITY_UMAL_BASE + 0x0198)
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/*
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* Interrupts, read only UMAL_DMAInterrupt
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*/
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#define UMAL_DMAInterrupt (PKUNITY_UMAL_BASE + 0x019c)
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/*
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* Commands for UMAL_CFG1 register
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*/
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#define UMAL_CFG1_TXENABLE FIELD(1, 1, 0)
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#define UMAL_CFG1_RXENABLE FIELD(1, 1, 2)
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#define UMAL_CFG1_TXFLOWCTL FIELD(1, 1, 4)
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#define UMAL_CFG1_RXFLOWCTL FIELD(1, 1, 5)
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#define UMAL_CFG1_CONFLPBK FIELD(1, 1, 8)
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#define UMAL_CFG1_RESET FIELD(1, 1, 31)
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#define UMAL_CFG1_CONFFLCTL (MAC_TX_FLOW_CTL | MAC_RX_FLOW_CTL)
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/*
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* Commands for UMAL_CFG2 register
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*/
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#define UMAL_CFG2_FULLDUPLEX FIELD(1, 1, 0)
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#define UMAL_CFG2_CRCENABLE FIELD(1, 1, 1)
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#define UMAL_CFG2_PADCRC FIELD(1, 1, 2)
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#define UMAL_CFG2_LENGTHCHECK FIELD(1, 1, 4)
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#define UMAL_CFG2_MODEMASK FMASK(2, 8)
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#define UMAL_CFG2_NIBBLEMODE FIELD(1, 2, 8)
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#define UMAL_CFG2_BYTEMODE FIELD(2, 2, 8)
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#define UMAL_CFG2_PREAMBLENMASK FMASK(4, 12)
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#define UMAL_CFG2_DEFPREAMBLEN FIELD(7, 4, 12)
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#define UMAL_CFG2_FD100 (UMAL_CFG2_DEFPREAMBLEN | UMAL_CFG2_NIBBLEMODE \
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| UMAL_CFG2_LENGTHCHECK | UMAL_CFG2_PADCRC \
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| UMAL_CFG2_CRCENABLE | UMAL_CFG2_FULLDUPLEX)
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#define UMAL_CFG2_FD1000 (UMAL_CFG2_DEFPREAMBLEN | UMAL_CFG2_BYTEMODE \
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| UMAL_CFG2_LENGTHCHECK | UMAL_CFG2_PADCRC \
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| UMAL_CFG2_CRCENABLE | UMAL_CFG2_FULLDUPLEX)
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#define UMAL_CFG2_HD100 (UMAL_CFG2_DEFPREAMBLEN | UMAL_CFG2_NIBBLEMODE \
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| UMAL_CFG2_LENGTHCHECK | UMAL_CFG2_PADCRC \
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| UMAL_CFG2_CRCENABLE)
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/*
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* Command for UMAL_IFCTRL register
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*/
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#define UMAL_IFCTRL_RESET FIELD(1, 1, 31)
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/*
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* Command for UMAL_MIICFG register
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*/
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#define UMAL_MIICFG_RESET FIELD(1, 1, 31)
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/*
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* Command for UMAL_MIICMD register
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*/
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#define UMAL_MIICMD_READ FIELD(1, 1, 0)
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/*
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* Command for UMAL_MIIIDCT register
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*/
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#define UMAL_MIIIDCT_BUSY FIELD(1, 1, 0)
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#define UMAL_MIIIDCT_NOTVALID FIELD(1, 1, 2)
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/*
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* Commands for DMATxCtrl regesters
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*/
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#define UMAL_DMA_Enable FIELD(1, 1, 0)
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/*
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* Commands for DMARxCtrl regesters
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*/
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#define UMAL_DMAIntrMask_ENABLEHALFWORD FIELD(1, 1, 16)
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/*
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* Command for DMARxStatus
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*/
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#define CLR_RX_BUS_ERR FIELD(1, 1, 3)
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#define CLR_RX_OVERFLOW FIELD(1, 1, 2)
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#define CLR_RX_PKT FIELD(1, 1, 0)
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/*
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* Command for DMATxStatus
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*/
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#define CLR_TX_BUS_ERR FIELD(1, 1, 3)
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#define CLR_TX_UNDERRUN FIELD(1, 1, 1)
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#define CLR_TX_PKT FIELD(1, 1, 0)
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/*
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* Commands for DMAIntrMask and DMAInterrupt register
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*/
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#define INT_RX_MASK FIELD(0xd, 4, 4)
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#define INT_TX_MASK FIELD(0xb, 4, 0)
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#define INT_RX_BUS_ERR FIELD(1, 1, 7)
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#define INT_RX_OVERFLOW FIELD(1, 1, 6)
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#define INT_RX_PKT FIELD(1, 1, 4)
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#define INT_TX_BUS_ERR FIELD(1, 1, 3)
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#define INT_TX_UNDERRUN FIELD(1, 1, 1)
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#define INT_TX_PKT FIELD(1, 1, 0)
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/*
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* MARCOS of UMAL's descriptors
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*/
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#define UMAL_DESC_PACKETSIZE_EMPTY FIELD(1, 1, 31)
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#define UMAL_DESC_PACKETSIZE_NONEMPTY FIELD(0, 1, 31)
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#define UMAL_DESC_PACKETSIZE_SIZEMASK FMASK(12, 0)
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