2024-09-09 08:52:07 +00:00
|
|
|
menu "Processor features"
|
|
|
|
|
|
|
|
|
|
choice
|
2024-09-09 08:57:42 +00:00
|
|
|
prompt "Endianness selection"
|
2024-09-09 08:52:07 +00:00
|
|
|
default CPU_LITTLE_ENDIAN
|
|
|
|
|
help
|
|
|
|
|
Some SuperH machines can be configured for either little or big
|
|
|
|
|
endian byte order. These modes require different kernels.
|
|
|
|
|
|
|
|
|
|
config CPU_LITTLE_ENDIAN
|
|
|
|
|
bool "Little Endian"
|
|
|
|
|
|
|
|
|
|
config CPU_BIG_ENDIAN
|
|
|
|
|
bool "Big Endian"
|
|
|
|
|
depends on !CPU_SH5
|
|
|
|
|
|
|
|
|
|
endchoice
|
|
|
|
|
|
|
|
|
|
config SH_FPU
|
|
|
|
|
def_bool y
|
|
|
|
|
prompt "FPU support"
|
|
|
|
|
depends on CPU_HAS_FPU
|
|
|
|
|
help
|
|
|
|
|
Selecting this option will enable support for SH processors that
|
|
|
|
|
have FPU units (ie, SH77xx).
|
|
|
|
|
|
|
|
|
|
This option must be set in order to enable the FPU.
|
|
|
|
|
|
|
|
|
|
config SH64_FPU_DENORM_FLUSH
|
|
|
|
|
bool "Flush floating point denorms to zero"
|
|
|
|
|
depends on SH_FPU && SUPERH64
|
|
|
|
|
|
|
|
|
|
config SH_FPU_EMU
|
|
|
|
|
def_bool n
|
|
|
|
|
prompt "FPU emulation support"
|
2024-09-09 08:57:42 +00:00
|
|
|
depends on !SH_FPU
|
2024-09-09 08:52:07 +00:00
|
|
|
help
|
|
|
|
|
Selecting this option will enable support for software FPU emulation.
|
|
|
|
|
Most SH-3 users will want to say Y here, whereas most SH-4 users will
|
|
|
|
|
want to say N.
|
|
|
|
|
|
|
|
|
|
config SH_DSP
|
|
|
|
|
def_bool y
|
|
|
|
|
prompt "DSP support"
|
|
|
|
|
depends on CPU_HAS_DSP
|
|
|
|
|
help
|
|
|
|
|
Selecting this option will enable support for SH processors that
|
|
|
|
|
have DSP units (ie, SH2-DSP, SH3-DSP, and SH4AL-DSP).
|
|
|
|
|
|
|
|
|
|
This option must be set in order to enable the DSP.
|
|
|
|
|
|
|
|
|
|
config SH_ADC
|
|
|
|
|
def_bool y
|
|
|
|
|
prompt "ADC support"
|
|
|
|
|
depends on CPU_SH3
|
|
|
|
|
help
|
|
|
|
|
Selecting this option will allow the Linux kernel to use SH3 on-chip
|
|
|
|
|
ADC module.
|
|
|
|
|
|
|
|
|
|
If unsure, say N.
|
|
|
|
|
|
|
|
|
|
config SH_STORE_QUEUES
|
|
|
|
|
bool "Support for Store Queues"
|
|
|
|
|
depends on CPU_SH4
|
|
|
|
|
help
|
|
|
|
|
Selecting this option will enable an in-kernel API for manipulating
|
|
|
|
|
the store queues integrated in the SH-4 processors.
|
|
|
|
|
|
|
|
|
|
config SPECULATIVE_EXECUTION
|
|
|
|
|
bool "Speculative subroutine return"
|
|
|
|
|
depends on CPU_SUBTYPE_SH7780 || CPU_SUBTYPE_SH7785 || CPU_SUBTYPE_SH7786
|
|
|
|
|
help
|
|
|
|
|
This enables support for a speculative instruction fetch for
|
|
|
|
|
subroutine return. There are various pitfalls associated with
|
|
|
|
|
this, as outlined in the SH7780 hardware manual.
|
|
|
|
|
|
|
|
|
|
If unsure, say N.
|
|
|
|
|
|
|
|
|
|
config SH64_ID2815_WORKAROUND
|
|
|
|
|
bool "Include workaround for SH5-101 cut2 silicon defect ID2815"
|
|
|
|
|
depends on CPU_SUBTYPE_SH5_101
|
|
|
|
|
|
|
|
|
|
config CPU_HAS_INTEVT
|
|
|
|
|
bool
|
|
|
|
|
|
|
|
|
|
config CPU_HAS_IPR_IRQ
|
|
|
|
|
bool
|
|
|
|
|
|
|
|
|
|
config CPU_HAS_SR_RB
|
|
|
|
|
bool
|
|
|
|
|
help
|
|
|
|
|
This will enable the use of SR.RB register bank usage. Processors
|
|
|
|
|
that are lacking this bit must have another method in place for
|
|
|
|
|
accomplishing what is taken care of by the banked registers.
|
|
|
|
|
|
|
|
|
|
See <file:Documentation/sh/register-banks.txt> for further
|
|
|
|
|
information on SR.RB and register banking in the kernel in general.
|
|
|
|
|
|
|
|
|
|
config CPU_HAS_PTEAEX
|
|
|
|
|
bool
|
|
|
|
|
|
|
|
|
|
config CPU_HAS_DSP
|
|
|
|
|
bool
|
|
|
|
|
|
|
|
|
|
config CPU_HAS_FPU
|
|
|
|
|
bool
|
|
|
|
|
|
|
|
|
|
endmenu
|
