430 lines
9.8 KiB
C
430 lines
9.8 KiB
C
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/*
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* Support for SCC external PCI
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*
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* (C) Copyright 2004-2007 TOSHIBA CORPORATION
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
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*/
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#undef DEBUG
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#include <linux/kernel.h>
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#include <linux/threads.h>
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#include <linux/pci.h>
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#include <linux/init.h>
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#include <linux/pci_regs.h>
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#include <linux/bootmem.h>
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#include <asm/io.h>
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#include <asm/irq.h>
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#include <asm/prom.h>
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#include <asm/pci-bridge.h>
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#include <asm/ppc-pci.h>
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#include "celleb_scc.h"
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#include "celleb_pci.h"
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#define MAX_PCI_DEVICES 32
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#define MAX_PCI_FUNCTIONS 8
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#define iob() __asm__ __volatile__("eieio; sync":::"memory")
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static inline PCI_IO_ADDR celleb_epci_get_epci_base(
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struct pci_controller *hose)
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{
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/*
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* Note:
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* Celleb epci uses cfg_addr as a base address for
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* epci control registers.
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*/
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return hose->cfg_addr;
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}
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static inline PCI_IO_ADDR celleb_epci_get_epci_cfg(
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struct pci_controller *hose)
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{
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/*
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* Note:
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* Celleb epci uses cfg_data as a base address for
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* configuration area for epci devices.
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*/
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return hose->cfg_data;
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}
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static inline void clear_and_disable_master_abort_interrupt(
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struct pci_controller *hose)
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{
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PCI_IO_ADDR epci_base;
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PCI_IO_ADDR reg;
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epci_base = celleb_epci_get_epci_base(hose);
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reg = epci_base + PCI_COMMAND;
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out_be32(reg, in_be32(reg) | (PCI_STATUS_REC_MASTER_ABORT << 16));
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}
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static int celleb_epci_check_abort(struct pci_controller *hose,
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PCI_IO_ADDR addr)
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{
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PCI_IO_ADDR reg;
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PCI_IO_ADDR epci_base;
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u32 val;
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iob();
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epci_base = celleb_epci_get_epci_base(hose);
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reg = epci_base + PCI_COMMAND;
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val = in_be32(reg);
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if (val & (PCI_STATUS_REC_MASTER_ABORT << 16)) {
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out_be32(reg,
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(val & 0xffff) | (PCI_STATUS_REC_MASTER_ABORT << 16));
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/* clear PCI Controller error, FRE, PMFE */
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reg = epci_base + SCC_EPCI_STATUS;
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out_be32(reg, SCC_EPCI_INT_PAI);
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reg = epci_base + SCC_EPCI_VCSR;
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val = in_be32(reg) & 0xffff;
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val |= SCC_EPCI_VCSR_FRE;
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out_be32(reg, val);
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reg = epci_base + SCC_EPCI_VISTAT;
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out_be32(reg, SCC_EPCI_VISTAT_PMFE);
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return PCIBIOS_DEVICE_NOT_FOUND;
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}
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return PCIBIOS_SUCCESSFUL;
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}
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static PCI_IO_ADDR celleb_epci_make_config_addr(struct pci_bus *bus,
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struct pci_controller *hose, unsigned int devfn, int where)
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{
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PCI_IO_ADDR addr;
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if (bus != hose->bus)
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addr = celleb_epci_get_epci_cfg(hose) +
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(((bus->number & 0xff) << 16)
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| ((devfn & 0xff) << 8)
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| (where & 0xff)
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| 0x01000000);
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else
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addr = celleb_epci_get_epci_cfg(hose) +
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(((devfn & 0xff) << 8) | (where & 0xff));
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pr_debug("EPCI: config_addr = 0x%p\n", addr);
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return addr;
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}
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static int celleb_epci_read_config(struct pci_bus *bus,
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unsigned int devfn, int where, int size, u32 *val)
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{
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PCI_IO_ADDR epci_base;
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PCI_IO_ADDR addr;
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struct pci_controller *hose = pci_bus_to_host(bus);
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/* allignment check */
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BUG_ON(where % size);
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if (!celleb_epci_get_epci_cfg(hose))
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return PCIBIOS_DEVICE_NOT_FOUND;
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if (bus->number == hose->first_busno && devfn == 0) {
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/* EPCI controller self */
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epci_base = celleb_epci_get_epci_base(hose);
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addr = epci_base + where;
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switch (size) {
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case 1:
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*val = in_8(addr);
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break;
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case 2:
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*val = in_be16(addr);
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break;
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case 4:
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*val = in_be32(addr);
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break;
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default:
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return PCIBIOS_DEVICE_NOT_FOUND;
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}
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} else {
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clear_and_disable_master_abort_interrupt(hose);
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addr = celleb_epci_make_config_addr(bus, hose, devfn, where);
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switch (size) {
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case 1:
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*val = in_8(addr);
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break;
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case 2:
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*val = in_le16(addr);
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break;
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case 4:
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*val = in_le32(addr);
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break;
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default:
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return PCIBIOS_DEVICE_NOT_FOUND;
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}
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}
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pr_debug("EPCI: "
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"addr=0x%p, devfn=0x%x, where=0x%x, size=0x%x, val=0x%x\n",
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addr, devfn, where, size, *val);
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return celleb_epci_check_abort(hose, NULL);
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}
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static int celleb_epci_write_config(struct pci_bus *bus,
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unsigned int devfn, int where, int size, u32 val)
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{
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PCI_IO_ADDR epci_base;
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PCI_IO_ADDR addr;
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struct pci_controller *hose = pci_bus_to_host(bus);
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/* allignment check */
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BUG_ON(where % size);
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if (!celleb_epci_get_epci_cfg(hose))
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return PCIBIOS_DEVICE_NOT_FOUND;
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if (bus->number == hose->first_busno && devfn == 0) {
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/* EPCI controller self */
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epci_base = celleb_epci_get_epci_base(hose);
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addr = epci_base + where;
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switch (size) {
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case 1:
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out_8(addr, val);
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break;
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case 2:
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out_be16(addr, val);
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break;
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case 4:
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out_be32(addr, val);
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break;
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default:
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return PCIBIOS_DEVICE_NOT_FOUND;
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}
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} else {
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clear_and_disable_master_abort_interrupt(hose);
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addr = celleb_epci_make_config_addr(bus, hose, devfn, where);
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switch (size) {
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case 1:
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out_8(addr, val);
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break;
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case 2:
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out_le16(addr, val);
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break;
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case 4:
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out_le32(addr, val);
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break;
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default:
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return PCIBIOS_DEVICE_NOT_FOUND;
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}
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}
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return celleb_epci_check_abort(hose, addr);
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}
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struct pci_ops celleb_epci_ops = {
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.read = celleb_epci_read_config,
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.write = celleb_epci_write_config,
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};
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/* to be moved in FW */
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static int __init celleb_epci_init(struct pci_controller *hose)
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{
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u32 val;
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PCI_IO_ADDR reg;
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PCI_IO_ADDR epci_base;
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int hwres = 0;
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epci_base = celleb_epci_get_epci_base(hose);
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/* PCI core reset(Internal bus and PCI clock) */
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reg = epci_base + SCC_EPCI_CKCTRL;
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val = in_be32(reg);
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if (val == 0x00030101)
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hwres = 1;
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else {
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val &= ~(SCC_EPCI_CKCTRL_CRST0 | SCC_EPCI_CKCTRL_CRST1);
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out_be32(reg, val);
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/* set PCI core clock */
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val = in_be32(reg);
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val |= (SCC_EPCI_CKCTRL_OCLKEN | SCC_EPCI_CKCTRL_LCLKEN);
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out_be32(reg, val);
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/* release PCI core reset (internal bus) */
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val = in_be32(reg);
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val |= SCC_EPCI_CKCTRL_CRST0;
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out_be32(reg, val);
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/* set PCI clock select */
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reg = epci_base + SCC_EPCI_CLKRST;
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val = in_be32(reg);
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val &= ~SCC_EPCI_CLKRST_CKS_MASK;
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val |= SCC_EPCI_CLKRST_CKS_2;
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out_be32(reg, val);
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/* set arbiter */
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reg = epci_base + SCC_EPCI_ABTSET;
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out_be32(reg, 0x0f1f001f); /* temporary value */
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/* buffer on */
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reg = epci_base + SCC_EPCI_CLKRST;
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val = in_be32(reg);
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val |= SCC_EPCI_CLKRST_BC;
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out_be32(reg, val);
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/* PCI clock enable */
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val = in_be32(reg);
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val |= SCC_EPCI_CLKRST_PCKEN;
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out_be32(reg, val);
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/* release PCI core reset (all) */
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reg = epci_base + SCC_EPCI_CKCTRL;
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val = in_be32(reg);
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val |= (SCC_EPCI_CKCTRL_CRST0 | SCC_EPCI_CKCTRL_CRST1);
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out_be32(reg, val);
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/* set base translation registers. (already set by Beat) */
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/* set base address masks. (already set by Beat) */
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}
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/* release interrupt masks and clear all interrupts */
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reg = epci_base + SCC_EPCI_INTSET;
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out_be32(reg, 0x013f011f); /* all interrupts enable */
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reg = epci_base + SCC_EPCI_VIENAB;
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val = SCC_EPCI_VIENAB_PMPEE | SCC_EPCI_VIENAB_PMFEE;
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out_be32(reg, val);
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reg = epci_base + SCC_EPCI_STATUS;
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out_be32(reg, 0xffffffff);
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reg = epci_base + SCC_EPCI_VISTAT;
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out_be32(reg, 0xffffffff);
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/* disable PCI->IB address translation */
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reg = epci_base + SCC_EPCI_VCSR;
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val = in_be32(reg);
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val &= ~(SCC_EPCI_VCSR_DR | SCC_EPCI_VCSR_AT);
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out_be32(reg, val);
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/* set base addresses. (no need to set?) */
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/* memory space, bus master enable */
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reg = epci_base + PCI_COMMAND;
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val = PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER;
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out_be32(reg, val);
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/* endian mode setup */
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reg = epci_base + SCC_EPCI_ECMODE;
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val = 0x00550155;
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out_be32(reg, val);
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/* set control option */
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reg = epci_base + SCC_EPCI_CNTOPT;
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val = in_be32(reg);
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val |= SCC_EPCI_CNTOPT_O2PMB;
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out_be32(reg, val);
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/* XXX: temporay: set registers for address conversion setup */
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reg = epci_base + SCC_EPCI_CNF10_REG;
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out_be32(reg, 0x80000008);
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reg = epci_base + SCC_EPCI_CNF14_REG;
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out_be32(reg, 0x40000008);
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reg = epci_base + SCC_EPCI_BAM0;
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out_be32(reg, 0x80000000);
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reg = epci_base + SCC_EPCI_BAM1;
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out_be32(reg, 0xe0000000);
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reg = epci_base + SCC_EPCI_PVBAT;
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out_be32(reg, 0x80000000);
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if (!hwres) {
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/* release external PCI reset */
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reg = epci_base + SCC_EPCI_CLKRST;
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val = in_be32(reg);
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val |= SCC_EPCI_CLKRST_PCIRST;
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out_be32(reg, val);
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}
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return 0;
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}
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static int __init celleb_setup_epci(struct device_node *node,
|
||
|
|
struct pci_controller *hose)
|
||
|
|
{
|
||
|
|
struct resource r;
|
||
|
|
|
||
|
|
pr_debug("PCI: celleb_setup_epci()\n");
|
||
|
|
|
||
|
|
/*
|
||
|
|
* Note:
|
||
|
|
* Celleb epci uses cfg_addr and cfg_data member of
|
||
|
|
* pci_controller structure in irregular way.
|
||
|
|
*
|
||
|
|
* cfg_addr is used to map for control registers of
|
||
|
|
* celleb epci.
|
||
|
|
*
|
||
|
|
* cfg_data is used for configuration area of devices
|
||
|
|
* on Celleb epci buses.
|
||
|
|
*/
|
||
|
|
|
||
|
|
if (of_address_to_resource(node, 0, &r))
|
||
|
|
goto error;
|
||
|
|
hose->cfg_addr = ioremap(r.start, resource_size(&r));
|
||
|
|
if (!hose->cfg_addr)
|
||
|
|
goto error;
|
||
|
|
pr_debug("EPCI: cfg_addr map 0x%016llx->0x%016lx + 0x%016llx\n",
|
||
|
|
r.start, (unsigned long)hose->cfg_addr, resource_size(&r));
|
||
|
|
|
||
|
|
if (of_address_to_resource(node, 2, &r))
|
||
|
|
goto error;
|
||
|
|
hose->cfg_data = ioremap(r.start, resource_size(&r));
|
||
|
|
if (!hose->cfg_data)
|
||
|
|
goto error;
|
||
|
|
pr_debug("EPCI: cfg_data map 0x%016llx->0x%016lx + 0x%016llx\n",
|
||
|
|
r.start, (unsigned long)hose->cfg_data, resource_size(&r));
|
||
|
|
|
||
|
|
hose->ops = &celleb_epci_ops;
|
||
|
|
celleb_epci_init(hose);
|
||
|
|
|
||
|
|
return 0;
|
||
|
|
|
||
|
|
error:
|
||
|
|
if (hose->cfg_addr)
|
||
|
|
iounmap(hose->cfg_addr);
|
||
|
|
|
||
|
|
if (hose->cfg_data)
|
||
|
|
iounmap(hose->cfg_data);
|
||
|
|
return 1;
|
||
|
|
}
|
||
|
|
|
||
|
|
struct celleb_phb_spec celleb_epci_spec __initdata = {
|
||
|
|
.setup = celleb_setup_epci,
|
||
|
|
.ops = &spiderpci_ops,
|
||
|
|
.iowa_init = &spiderpci_iowa_init,
|
||
|
|
.iowa_data = (void *)0,
|
||
|
|
};
|