2024-09-09 08:52:07 +00:00
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/*
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* Author: MontaVista Software, Inc.
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2024-09-09 08:57:42 +00:00
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* source@mvista.com
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2024-09-09 08:52:07 +00:00
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*
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* Copyright 2001-2006 MontaVista Software Inc.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*
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* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
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* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
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* TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
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* USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 675 Mass Ave, Cambridge, MA 02139, USA.
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*/
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#ifndef __ASM_TXX9_TX4927_H
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#define __ASM_TXX9_TX4927_H
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#include <linux/types.h>
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#include <linux/io.h>
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#include <asm/txx9irq.h>
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#include <asm/txx9/tx4927pcic.h>
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#ifdef CONFIG_64BIT
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#define TX4927_REG_BASE 0xffffffffff1f0000UL
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#else
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#define TX4927_REG_BASE 0xff1f0000UL
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#endif
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#define TX4927_REG_SIZE 0x00010000
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#define TX4927_SDRAMC_REG (TX4927_REG_BASE + 0x8000)
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#define TX4927_EBUSC_REG (TX4927_REG_BASE + 0x9000)
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#define TX4927_DMA_REG (TX4927_REG_BASE + 0xb000)
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#define TX4927_PCIC_REG (TX4927_REG_BASE + 0xd000)
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#define TX4927_CCFG_REG (TX4927_REG_BASE + 0xe000)
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#define TX4927_IRC_REG (TX4927_REG_BASE + 0xf600)
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#define TX4927_NR_TMR 3
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#define TX4927_TMR_REG(ch) (TX4927_REG_BASE + 0xf000 + (ch) * 0x100)
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#define TX4927_NR_SIO 2
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#define TX4927_SIO_REG(ch) (TX4927_REG_BASE + 0xf300 + (ch) * 0x100)
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#define TX4927_PIO_REG (TX4927_REG_BASE + 0xf500)
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#define TX4927_ACLC_REG (TX4927_REG_BASE + 0xf700)
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#define TX4927_IR_ECCERR 0
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#define TX4927_IR_WTOERR 1
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#define TX4927_NUM_IR_INT 6
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#define TX4927_IR_INT(n) (2 + (n))
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#define TX4927_NUM_IR_SIO 2
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#define TX4927_IR_SIO(n) (8 + (n))
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#define TX4927_NUM_IR_DMA 4
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#define TX4927_IR_DMA(n) (10 + (n))
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#define TX4927_IR_PIO 14
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#define TX4927_IR_PDMAC 15
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#define TX4927_IR_PCIC 16
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#define TX4927_NUM_IR_TMR 3
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#define TX4927_IR_TMR(n) (17 + (n))
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#define TX4927_IR_PCIERR 22
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#define TX4927_IR_PCIPME 23
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#define TX4927_IR_ACLC 24
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#define TX4927_IR_ACLCPME 25
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#define TX4927_NUM_IR 32
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#define TX4927_IRC_INT 2 /* IP[2] in Status register */
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#define TX4927_NUM_PIO 16
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struct tx4927_sdramc_reg {
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u64 cr[4];
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u64 unused0[4];
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u64 tr;
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u64 unused1[2];
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u64 cmd;
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};
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struct tx4927_ebusc_reg {
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u64 cr[8];
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};
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struct tx4927_ccfg_reg {
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u64 ccfg;
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u64 crir;
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u64 pcfg;
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u64 toea;
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u64 clkctr;
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u64 unused0;
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u64 garbc;
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u64 unused1;
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u64 unused2;
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u64 ramp;
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};
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/*
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* CCFG
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*/
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/* CCFG : Chip Configuration */
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#define TX4927_CCFG_WDRST 0x0000020000000000ULL
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#define TX4927_CCFG_WDREXEN 0x0000010000000000ULL
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#define TX4927_CCFG_BCFG_MASK 0x000000ff00000000ULL
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#define TX4927_CCFG_TINTDIS 0x01000000
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#define TX4927_CCFG_PCI66 0x00800000
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#define TX4927_CCFG_PCIMODE 0x00400000
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#define TX4927_CCFG_DIVMODE_MASK 0x000e0000
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#define TX4927_CCFG_DIVMODE_8 (0x0 << 17)
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#define TX4927_CCFG_DIVMODE_12 (0x1 << 17)
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#define TX4927_CCFG_DIVMODE_16 (0x2 << 17)
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#define TX4927_CCFG_DIVMODE_10 (0x3 << 17)
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#define TX4927_CCFG_DIVMODE_2 (0x4 << 17)
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#define TX4927_CCFG_DIVMODE_3 (0x5 << 17)
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#define TX4927_CCFG_DIVMODE_4 (0x6 << 17)
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#define TX4927_CCFG_DIVMODE_2_5 (0x7 << 17)
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#define TX4927_CCFG_BEOW 0x00010000
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#define TX4927_CCFG_WR 0x00008000
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#define TX4927_CCFG_TOE 0x00004000
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#define TX4927_CCFG_PCIARB 0x00002000
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#define TX4927_CCFG_PCIDIVMODE_MASK 0x00001800
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#define TX4927_CCFG_PCIDIVMODE_2_5 0x00000000
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#define TX4927_CCFG_PCIDIVMODE_3 0x00000800
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#define TX4927_CCFG_PCIDIVMODE_5 0x00001000
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#define TX4927_CCFG_PCIDIVMODE_6 0x00001800
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#define TX4927_CCFG_SYSSP_MASK 0x000000c0
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#define TX4927_CCFG_ENDIAN 0x00000004
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#define TX4927_CCFG_HALT 0x00000002
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#define TX4927_CCFG_ACEHOLD 0x00000001
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#define TX4927_CCFG_W1CBITS (TX4927_CCFG_WDRST | TX4927_CCFG_BEOW)
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/* PCFG : Pin Configuration */
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#define TX4927_PCFG_SDCLKDLY_MASK 0x30000000
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#define TX4927_PCFG_SDCLKDLY(d) ((d)<<28)
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#define TX4927_PCFG_SYSCLKEN 0x08000000
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#define TX4927_PCFG_SDCLKEN_ALL 0x07800000
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#define TX4927_PCFG_SDCLKEN(ch) (0x00800000<<(ch))
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#define TX4927_PCFG_PCICLKEN_ALL 0x003f0000
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#define TX4927_PCFG_PCICLKEN(ch) (0x00010000<<(ch))
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#define TX4927_PCFG_SEL2 0x00000200
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#define TX4927_PCFG_SEL1 0x00000100
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#define TX4927_PCFG_DMASEL_ALL 0x000000ff
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#define TX4927_PCFG_DMASEL0_MASK 0x00000003
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#define TX4927_PCFG_DMASEL1_MASK 0x0000000c
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#define TX4927_PCFG_DMASEL2_MASK 0x00000030
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#define TX4927_PCFG_DMASEL3_MASK 0x000000c0
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#define TX4927_PCFG_DMASEL0_DRQ0 0x00000000
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#define TX4927_PCFG_DMASEL0_SIO1 0x00000001
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#define TX4927_PCFG_DMASEL0_ACL0 0x00000002
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#define TX4927_PCFG_DMASEL0_ACL2 0x00000003
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#define TX4927_PCFG_DMASEL1_DRQ1 0x00000000
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#define TX4927_PCFG_DMASEL1_SIO1 0x00000004
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#define TX4927_PCFG_DMASEL1_ACL1 0x00000008
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#define TX4927_PCFG_DMASEL1_ACL3 0x0000000c
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#define TX4927_PCFG_DMASEL2_DRQ2 0x00000000 /* SEL2=0 */
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#define TX4927_PCFG_DMASEL2_SIO0 0x00000010 /* SEL2=0 */
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#define TX4927_PCFG_DMASEL2_ACL1 0x00000000 /* SEL2=1 */
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#define TX4927_PCFG_DMASEL2_ACL2 0x00000020 /* SEL2=1 */
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#define TX4927_PCFG_DMASEL2_ACL0 0x00000030 /* SEL2=1 */
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#define TX4927_PCFG_DMASEL3_DRQ3 0x00000000
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#define TX4927_PCFG_DMASEL3_SIO0 0x00000040
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#define TX4927_PCFG_DMASEL3_ACL3 0x00000080
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#define TX4927_PCFG_DMASEL3_ACL1 0x000000c0
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/* CLKCTR : Clock Control */
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#define TX4927_CLKCTR_ACLCKD 0x02000000
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#define TX4927_CLKCTR_PIOCKD 0x01000000
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#define TX4927_CLKCTR_DMACKD 0x00800000
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#define TX4927_CLKCTR_PCICKD 0x00400000
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#define TX4927_CLKCTR_TM0CKD 0x00100000
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#define TX4927_CLKCTR_TM1CKD 0x00080000
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#define TX4927_CLKCTR_TM2CKD 0x00040000
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#define TX4927_CLKCTR_SIO0CKD 0x00020000
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#define TX4927_CLKCTR_SIO1CKD 0x00010000
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#define TX4927_CLKCTR_ACLRST 0x00000200
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#define TX4927_CLKCTR_PIORST 0x00000100
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#define TX4927_CLKCTR_DMARST 0x00000080
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#define TX4927_CLKCTR_PCIRST 0x00000040
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#define TX4927_CLKCTR_TM0RST 0x00000010
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#define TX4927_CLKCTR_TM1RST 0x00000008
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#define TX4927_CLKCTR_TM2RST 0x00000004
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#define TX4927_CLKCTR_SIO0RST 0x00000002
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#define TX4927_CLKCTR_SIO1RST 0x00000001
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#define tx4927_sdramcptr \
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((struct tx4927_sdramc_reg __iomem *)TX4927_SDRAMC_REG)
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#define tx4927_pcicptr \
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((struct tx4927_pcic_reg __iomem *)TX4927_PCIC_REG)
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#define tx4927_ccfgptr \
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((struct tx4927_ccfg_reg __iomem *)TX4927_CCFG_REG)
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#define tx4927_ebuscptr \
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((struct tx4927_ebusc_reg __iomem *)TX4927_EBUSC_REG)
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#define tx4927_pioptr ((struct txx9_pio_reg __iomem *)TX4927_PIO_REG)
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#define TX4927_REV_PCODE() \
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((__u32)__raw_readq(&tx4927_ccfgptr->crir) >> 16)
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#define TX4927_SDRAMC_CR(ch) __raw_readq(&tx4927_sdramcptr->cr[(ch)])
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#define TX4927_SDRAMC_BA(ch) ((TX4927_SDRAMC_CR(ch) >> 49) << 21)
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#define TX4927_SDRAMC_SIZE(ch) \
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((((TX4927_SDRAMC_CR(ch) >> 33) & 0x7fff) + 1) << 21)
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#define TX4927_EBUSC_CR(ch) __raw_readq(&tx4927_ebuscptr->cr[(ch)])
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#define TX4927_EBUSC_BA(ch) ((TX4927_EBUSC_CR(ch) >> 48) << 20)
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#define TX4927_EBUSC_SIZE(ch) \
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(0x00100000 << ((unsigned long)(TX4927_EBUSC_CR(ch) >> 8) & 0xf))
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#define TX4927_EBUSC_WIDTH(ch) \
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(64 >> ((__u32)(TX4927_EBUSC_CR(ch) >> 20) & 0x3))
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/* utilities */
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static inline void txx9_clear64(__u64 __iomem *adr, __u64 bits)
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{
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#ifdef CONFIG_32BIT
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unsigned long flags;
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local_irq_save(flags);
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#endif
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____raw_writeq(____raw_readq(adr) & ~bits, adr);
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#ifdef CONFIG_32BIT
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local_irq_restore(flags);
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#endif
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}
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static inline void txx9_set64(__u64 __iomem *adr, __u64 bits)
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{
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#ifdef CONFIG_32BIT
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unsigned long flags;
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local_irq_save(flags);
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#endif
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____raw_writeq(____raw_readq(adr) | bits, adr);
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#ifdef CONFIG_32BIT
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local_irq_restore(flags);
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#endif
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}
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/* These functions are not interrupt safe. */
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static inline void tx4927_ccfg_clear(__u64 bits)
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{
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____raw_writeq(____raw_readq(&tx4927_ccfgptr->ccfg)
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& ~(TX4927_CCFG_W1CBITS | bits),
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&tx4927_ccfgptr->ccfg);
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}
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static inline void tx4927_ccfg_set(__u64 bits)
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{
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____raw_writeq((____raw_readq(&tx4927_ccfgptr->ccfg)
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& ~TX4927_CCFG_W1CBITS) | bits,
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&tx4927_ccfgptr->ccfg);
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}
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static inline void tx4927_ccfg_change(__u64 change, __u64 new)
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{
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____raw_writeq((____raw_readq(&tx4927_ccfgptr->ccfg)
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& ~(TX4927_CCFG_W1CBITS | change)) |
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new,
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&tx4927_ccfgptr->ccfg);
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}
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unsigned int tx4927_get_mem_size(void);
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void tx4927_wdt_init(void);
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void tx4927_setup(void);
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void tx4927_time_init(unsigned int tmrnr);
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void tx4927_sio_init(unsigned int sclk, unsigned int cts_mask);
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int tx4927_report_pciclk(void);
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int tx4927_pciclk66_setup(void);
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void tx4927_setup_pcierr_irq(void);
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void tx4927_irq_init(void);
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void tx4927_mtd_init(int ch);
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void tx4927_dmac_init(int memcpy_chan);
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void tx4927_aclc_init(unsigned int dma_chan_out, unsigned int dma_chan_in);
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#endif /* __ASM_TXX9_TX4927_H */
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