2024-09-09 08:52:07 +00:00
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/*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 2005-2009 Cavium Networks
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*/
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#ifndef __PCI_OCTEON_H__
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#define __PCI_OCTEON_H__
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#include <linux/pci.h>
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/*
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* The physical memory base mapped by BAR1. 256MB at the end of the
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* first 4GB.
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*/
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#define CVMX_PCIE_BAR1_PHYS_BASE ((1ull << 32) - (1ull << 28))
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#define CVMX_PCIE_BAR1_PHYS_SIZE (1ull << 28)
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/*
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2024-09-09 08:57:42 +00:00
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* The RC base of BAR1. gen1 has a 39-bit BAR2, gen2 has 41-bit BAR2,
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2024-09-09 08:52:07 +00:00
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* place BAR1 so it is the same for both.
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*/
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#define CVMX_PCIE_BAR1_RC_BASE (1ull << 41)
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/*
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* pcibios_map_irq() is defined inside pci-octeon.c. All it does is
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* call the Octeon specific version pointed to by this variable. This
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* function needs to change for PCI or PCIe based hosts.
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*/
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extern int (*octeon_pcibios_map_irq)(const struct pci_dev *dev,
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u8 slot, u8 pin);
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/*
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* For PCI (not PCIe) the BAR2 base address.
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*/
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#define OCTEON_BAR2_PCI_ADDRESS 0x8000000000ull
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/*
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* For PCI (not PCIe) the base of the memory mapped by BAR1
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*/
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extern u64 octeon_bar1_pci_phys;
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/*
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* The following defines are used when octeon_dma_bar_type =
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* OCTEON_DMA_BAR_TYPE_BIG
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*/
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#define OCTEON_PCI_BAR1_HOLE_BITS 5
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#define OCTEON_PCI_BAR1_HOLE_SIZE (1ul<<(OCTEON_PCI_BAR1_HOLE_BITS+3))
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enum octeon_dma_bar_type {
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OCTEON_DMA_BAR_TYPE_INVALID,
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OCTEON_DMA_BAR_TYPE_SMALL,
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OCTEON_DMA_BAR_TYPE_BIG,
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OCTEON_DMA_BAR_TYPE_PCIE,
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OCTEON_DMA_BAR_TYPE_PCIE2
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};
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/*
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* This tells the DMA mapping system in dma-octeon.c how to map PCI
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* DMA addresses.
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*/
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extern enum octeon_dma_bar_type octeon_dma_bar_type;
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#endif
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